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Date: Sun, 13 Feb 2022 21:42:11 -0600 From: Samuel Holland <samuel@...lland.org> To: Heiko Stuebner <heiko@...ech.de>, palmer@...belt.com, paul.walmsley@...ive.com, aou@...s.berkeley.edu Cc: linux-riscv@...ts.infradead.org, devicetree@...r.kernel.org, linux-kernel@...r.kernel.org, robh+dt@...nel.org, wefu@...hat.com, liush@...winnertech.com, guoren@...nel.org, atishp@...shpatra.org, anup@...infault.org, drew@...gleboard.org, hch@....de, arnd@...db.de, wens@...e.org, maxime@...no.tech, gfavor@...tanamicro.com, andrea.mondelli@...wei.com, behrensj@....edu, xinhaoqu@...wei.com, huffman@...ence.com, mick@....forth.gr, allen.baum@...erantotech.com, jscheid@...tanamicro.com, rtrauben@...il.com, cmuellner@...ux.com, philipp.tomsich@...ll.eu Subject: Re: [PATCH v6 14/14] riscv: add memory-type errata for T-Head On 2/9/22 6:38 AM, Heiko Stuebner wrote: > Some current cpus based on T-Head cores implement memory-types > way different than described in the svpbmt spec even going > so far as using PTE bits marked as reserved. > > Add the T-Head vendor-id and necessary errata code to > replace the affected instructions. > > Signed-off-by: Heiko Stuebner <heiko@...ech.de> Tested-by: Samuel Holland <samuel@...lland.org>
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