linux-kernel - Re: [PATCH v2 11/11] ARM: dts: armada-385.dtsi: Add definitions for PCIe legacy INTx interrupts

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Message-ID: <87wnhxjxlq.fsf@BL-laptop>
Date:   Mon, 14 Feb 2022 16:07:13 +0100
From:   Gregory CLEMENT <gregory.clement@...tlin.com>
To:     Pali Rohár <pali@...nel.org>,
        Lorenzo Pieralisi <lorenzo.pieralisi@....com>,
        Bjorn Helgaas <bhelgaas@...gle.com>,
        Rob Herring <robh+dt@...nel.org>,
        Thomas Petazzoni <thomas.petazzoni@...tlin.com>,
        Krzysztof Wilczyński <kw@...ux.com>,
        Marek Behún <kabel@...nel.org>,
        Russell King <rmk+kernel@...linux.org.uk>,
        Andrew Lunn <andrew@...n.ch>
Cc:     linux-pci@...r.kernel.org, linux-kernel@...r.kernel.org,
        linux-arm-kernel@...ts.infradead.org, devicetree@...r.kernel.org
Subject: Re: [PATCH v2 11/11] ARM: dts: armada-385.dtsi: Add definitions for
 PCIe legacy INTx interrupts

Hello Pali,

> With this change legacy INTA, INTB, INTC and INTD interrupts are reported
> separately and not mixed into one Linux virq source anymore.
>
> Signed-off-by: Pali Rohár <pali@...nel.org>
> ---
>  arch/arm/boot/dts/armada-385.dtsi | 52 ++++++++++++++++++++++++++-----

Is there any reason for not doing the same change in armada-380.dtsi ?

Grégory

>  1 file changed, 44 insertions(+), 8 deletions(-)
>
> diff --git a/arch/arm/boot/dts/armada-385.dtsi b/arch/arm/boot/dts/armada-385.dtsi
> index f0022d10c715..83392b92dae2 100644
> --- a/arch/arm/boot/dts/armada-385.dtsi
> +++ b/arch/arm/boot/dts/armada-385.dtsi
> @@ -69,16 +69,25 @@
>  				reg = <0x0800 0 0 0 0>;
>  				#address-cells = <3>;
>  				#size-cells = <2>;
> +				interrupt-names = "intx";
> +				interrupts-extended = <&gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
>  				#interrupt-cells = <1>;
>  				ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
>  					  0x81000000 0 0 0x81000000 0x1 0 1 0>;
>  				bus-range = <0x00 0xff>;
> -				interrupt-map-mask = <0 0 0 0>;
> -				interrupt-map = <0 0 0 0 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
> +				interrupt-map-mask = <0 0 0 7>;
> +				interrupt-map = <0 0 0 1 &pcie1_intc 0>,
> +						<0 0 0 2 &pcie1_intc 1>,
> +						<0 0 0 3 &pcie1_intc 2>,
> +						<0 0 0 4 &pcie1_intc 3>;
>  				marvell,pcie-port = <0>;
>  				marvell,pcie-lane = <0>;
>  				clocks = <&gateclk 8>;
>  				status = "disabled";
> +				pcie1_intc: interrupt-controller {
> +					interrupt-controller;
> +					#interrupt-cells = <1>;
> +				};
>  			};
>  
>  			/* x1 port */
> @@ -88,16 +97,25 @@
>  				reg = <0x1000 0 0 0 0>;
>  				#address-cells = <3>;
>  				#size-cells = <2>;
> +				interrupt-names = "intx";
> +				interrupts-extended = <&gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
>  				#interrupt-cells = <1>;
>  				ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
>  					  0x81000000 0 0 0x81000000 0x2 0 1 0>;
>  				bus-range = <0x00 0xff>;
> -				interrupt-map-mask = <0 0 0 0>;
> -				interrupt-map = <0 0 0 0 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
> +				interrupt-map-mask = <0 0 0 7>;
> +				interrupt-map = <0 0 0 1 &pcie2_intc 0>,
> +						<0 0 0 2 &pcie2_intc 1>,
> +						<0 0 0 3 &pcie2_intc 2>,
> +						<0 0 0 4 &pcie2_intc 3>;
>  				marvell,pcie-port = <1>;
>  				marvell,pcie-lane = <0>;
>  				clocks = <&gateclk 5>;
>  				status = "disabled";
> +				pcie2_intc: interrupt-controller {
> +					interrupt-controller;
> +					#interrupt-cells = <1>;
> +				};
>  			};
>  
>  			/* x1 port */
> @@ -107,16 +125,25 @@
>  				reg = <0x1800 0 0 0 0>;
>  				#address-cells = <3>;
>  				#size-cells = <2>;
> +				interrupt-names = "intx";
> +				interrupts-extended = <&gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
>  				#interrupt-cells = <1>;
>  				ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0
>  					  0x81000000 0 0 0x81000000 0x3 0 1 0>;
>  				bus-range = <0x00 0xff>;
> -				interrupt-map-mask = <0 0 0 0>;
> -				interrupt-map = <0 0 0 0 &gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
> +				interrupt-map-mask = <0 0 0 7>;
> +				interrupt-map = <0 0 0 1 &pcie3_intc 0>,
> +						<0 0 0 2 &pcie3_intc 1>,
> +						<0 0 0 3 &pcie3_intc 2>,
> +						<0 0 0 4 &pcie3_intc 3>;
>  				marvell,pcie-port = <2>;
>  				marvell,pcie-lane = <0>;
>  				clocks = <&gateclk 6>;
>  				status = "disabled";
> +				pcie3_intc: interrupt-controller {
> +					interrupt-controller;
> +					#interrupt-cells = <1>;
> +				};
>  			};
>  
>  			/*
> @@ -129,16 +156,25 @@
>  				reg = <0x2000 0 0 0 0>;
>  				#address-cells = <3>;
>  				#size-cells = <2>;
> +				interrupt-names = "intx";
> +				interrupts-extended = <&gic GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
>  				#interrupt-cells = <1>;
>  				ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0
>  					  0x81000000 0 0 0x81000000 0x4 0 1 0>;
>  				bus-range = <0x00 0xff>;
> -				interrupt-map-mask = <0 0 0 0>;
> -				interrupt-map = <0 0 0 0 &gic GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
> +				interrupt-map-mask = <0 0 0 7>;
> +				interrupt-map = <0 0 0 1 &pcie4_intc 0>,
> +						<0 0 0 2 &pcie4_intc 1>,
> +						<0 0 0 3 &pcie4_intc 2>,
> +						<0 0 0 4 &pcie4_intc 3>;
>  				marvell,pcie-port = <3>;
>  				marvell,pcie-lane = <0>;
>  				clocks = <&gateclk 7>;
>  				status = "disabled";
> +				pcie4_intc: interrupt-controller {
> +					interrupt-controller;
> +					#interrupt-cells = <1>;
> +				};
>  			};
>  		};
>  	};
> -- 
> 2.20.1
>

-- 
Gregory Clement, Bootlin
Embedded Linux and Kernel engineering
http://bootlin.com