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Message-ID: <7da33ef9-67a4-343f-e97c-02d6bc40f2a9@photo-meter.com>
Date: Mon, 14 Feb 2022 16:34:42 +0100
From: Michael Anochin <anochin@...to-meter.com>
To: linux-kernel@...r.kernel.org
Subject: Re: [PATCH 5.16 009/200] can: m_can: m_can_fifo_{read,write}: dont
read or write from/to FIFO if length is 0
There is no -22 error message now. Tested with "cansend can0 123#"
But now it floods continuous from __skb_queue_add_sort:
[ xxx.xxx] tcan4x5x spi0.0 can0: __skb_queue_add_sort: pos=0x000000,
new=0x000000, diff= 0, queue_len=1
Only modprobe -r tcan4x5x or reboot helps
Hardware: RPI4 board with tcan4550 on spi0
Kernel 5.17.0-rc3-v7l+
from https://github.com/raspberrypi/linux/tree/rpi-5.17.y
Am 31.01.2022 um 11:54 schrieb Greg Kroah-Hartman:
> From: Marc Kleine-Budde <mkl@...gutronix.de>
>
> commit db72589c49fd260bfc99c7160c079675bc7417af upstream.
>
> In order to optimize FIFO access, especially on m_can cores attached
> to slow busses like SPI, in patch
>
> | e39381770ec9 ("can: m_can: Disable IRQs on FIFO bus errors")
>
> bulk read/write support has been added to the m_can_fifo_{read,write}
> functions.
>
> That change leads to the tcan driver to call
> regmap_bulk_{read,write}() with a length of 0 (for CAN frames with 0
> data length). regmap treats this as an error:
>
> | tcan4x5x spi1.0 tcan4x5x0: FIFO write returned -22
>
> This patch fixes the problem by not calling the
> cdev->ops->{read,write)_fifo() in case of a 0 length read/write.
>
> Fixes: e39381770ec9 ("can: m_can: Disable IRQs on FIFO bus errors")
> Link: https://lore.kernel.org/all/20220114155751.2651888-1-mkl@pengutronix.de
> Cc: stable@...r.kernel.org
> Cc: Matt Kline <matt@...bashing.io>
> Cc: Chandrasekar Ramakrishnan <rcsekar@...sung.com>
> Reported-by: Michael Anochin <anochin@...to-meter.com>
> Signed-off-by: Marc Kleine-Budde <mkl@...gutronix.de>
> Signed-off-by: Greg Kroah-Hartman <gregkh@...uxfoundation.org>
> ---
> drivers/net/can/m_can/m_can.c | 6 ++++++
> 1 file changed, 6 insertions(+)
>
> --- a/drivers/net/can/m_can/m_can.c
> +++ b/drivers/net/can/m_can/m_can.c
> @@ -336,6 +336,9 @@ m_can_fifo_read(struct m_can_classdev *c
> u32 addr_offset = cdev->mcfg[MRAM_RXF0].off + fgi * RXF0_ELEMENT_SIZE +
> offset;
>
> + if (val_count == 0)
> + return 0;
> +
> return cdev->ops->read_fifo(cdev, addr_offset, val, val_count);
> }
>
> @@ -346,6 +349,9 @@ m_can_fifo_write(struct m_can_classdev *
> u32 addr_offset = cdev->mcfg[MRAM_TXB].off + fpi * TXB_ELEMENT_SIZE +
> offset;
>
> + if (val_count == 0)
> + return 0;
> +
> return cdev->ops->write_fifo(cdev, addr_offset, val, val_count);
> }
>
>
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