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Message-Id: <1644821540-17928-1-git-send-email-quic_rohiagar@quicinc.com>
Date: Mon, 14 Feb 2022 12:22:20 +0530
From: Rohit Agarwal <quic_rohiagar@...cinc.com>
To: agross@...nel.org, bjorn.andersson@...aro.org,
mturquette@...libre.com, sboyd@...nel.org, robh+dt@...nel.org,
jassisinghbrar@...il.com, linux@...linux.org.uk, mani@...nel.org,
linus.walleij@...aro.org, dianders@...omium.org
Cc: linux-arm-msm@...r.kernel.org, linux-clk@...r.kernel.org,
devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
linux-arm-kernel@...ts.infradead.org,
Rohit Agarwal <quic_rohiagar@...cinc.com>
Subject: [PATCH 0/8] Add APCS support for SDX65
Hello,
This series adds APCS mailbox and clock support for SDX65. The APCS IP
in SDX65 provides IPC and clock functionalities. Hence, mailbox support
is added to the "qcom-apcs-ipc-mailbox" driver and a dedicated clock
driver "apcs-sdx65" is added.
Thanks,
Rohit
Rohit Agarwal (8):
dt-bindings: mailbox: Add binding for SDX65 APCS
mailbox: qcom: Add support for SDX65 APCS IPC
dt-bindings: clock: Add A7 PLL binding for SDX65
clk: qcom: Add A7 PLL support for SDX65
ARM: dts: qcom: sdx65: Add support for A7 PLL clock
ARM: dts: qcom: sdx65: Add support for APCS block
clk: qcom: Add SDX65 APCS clock controller support
ARM: configs: qcom_defconfig: Enable SDX65 APCS clock
.../devicetree/bindings/clock/qcom,a7pll.yaml | 3 +-
.../bindings/mailbox/qcom,apcs-kpss-global.yaml | 1 +
arch/arm/boot/dts/qcom-sdx65.dtsi | 17 +++
arch/arm/configs/qcom_defconfig | 1 +
drivers/clk/qcom/Kconfig | 15 ++-
drivers/clk/qcom/Makefile | 1 +
drivers/clk/qcom/a7-pll.c | 1 +
drivers/clk/qcom/apcs-sdx65.c | 130 +++++++++++++++++++++
drivers/mailbox/qcom-apcs-ipc-mailbox.c | 5 +
9 files changed, 170 insertions(+), 4 deletions(-)
create mode 100644 drivers/clk/qcom/apcs-sdx65.c
--
2.7.4
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