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Message-ID: <20220214083409.GB3494@thinkpad>
Date: Mon, 14 Feb 2022 14:04:09 +0530
From: Manivannan Sadhasivam <manivannan.sadhasivam@...aro.org>
To: Rohit Agarwal <quic_rohiagar@...cinc.com>
Cc: agross@...nel.org, bjorn.andersson@...aro.org,
jassisinghbrar@...il.com, linux-arm-msm@...r.kernel.org,
linux-kernel@...r.kernel.org
Subject: Re: [PATCH 2/8] mailbox: qcom: Add support for SDX65 APCS IPC
On Mon, Feb 14, 2022 at 12:25:55PM +0530, Rohit Agarwal wrote:
> In SDX65, the IPC bits are located in the APCS GCC block. Also, this block
> can provide clock functionality. Hence, add support for IPC with correct
> offset and name of the clock provider.
>
> Signed-off-by: Rohit Agarwal <quic_rohiagar@...cinc.com>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@...aro.org>
Thanks,
Mani
> ---
> drivers/mailbox/qcom-apcs-ipc-mailbox.c | 5 +++++
> 1 file changed, 5 insertions(+)
>
> diff --git a/drivers/mailbox/qcom-apcs-ipc-mailbox.c b/drivers/mailbox/qcom-apcs-ipc-mailbox.c
> index 9325d2a..3f8612c 100644
> --- a/drivers/mailbox/qcom-apcs-ipc-mailbox.c
> +++ b/drivers/mailbox/qcom-apcs-ipc-mailbox.c
> @@ -53,6 +53,10 @@ static const struct qcom_apcs_ipc_data sdx55_apcs_data = {
> .offset = 0x1008, .clk_name = "qcom-sdx55-acps-clk"
> };
>
> +static const struct qcom_apcs_ipc_data sdx65_apcs_data = {
> + .offset = 0x1008, .clk_name = "qcom-sdx65-acps-clk"
> +};
> +
> static const struct regmap_config apcs_regmap_config = {
> .reg_bits = 32,
> .reg_stride = 4,
> @@ -159,6 +163,7 @@ static const struct of_device_id qcom_apcs_ipc_of_match[] = {
> { .compatible = "qcom,sm8150-apss-shared", .data = &apps_shared_apcs_data },
> { .compatible = "qcom,sm6115-apcs-hmss-global", .data = &msm8994_apcs_data },
> { .compatible = "qcom,sdx55-apcs-gcc", .data = &sdx55_apcs_data },
> + { .compatible = "qcom,sdx65-apcs-gcc", .data = &sdx65_apcs_data },
> {}
> };
> MODULE_DEVICE_TABLE(of, qcom_apcs_ipc_of_match);
> --
> 2.7.4
>
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