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Message-ID: <6fae1b06-f275-fc11-8a3f-92fd7c666396@redhat.com>
Date: Tue, 15 Feb 2022 07:55:53 -0800
From: Tom Rix <trix@...hat.com>
To: Tianfei zhang <tianfei.zhang@...el.com>, hao.wu@...el.com,
mdf@...nel.org, yilun.xu@...el.com, linux-fpga@...r.kernel.org,
linux-doc@...r.kernel.org, linux-kernel@...r.kernel.org
Cc: corbet@....net, Matthew Gerlach <matthew.gerlach@...ux.intel.com>
Subject: Re: [PATCH v1 5/7] drivers: fpga: dfl: handle empty port list
On 2/14/22 3:26 AM, Tianfei zhang wrote:
> From: Matthew Gerlach <matthew.gerlach@...ux.intel.com>
>
> Not all FPGA designs managed by the DFL driver have a port.
> In these cases, don't write the Port Access Control register
> when enabling SRIOV.
Drop the 'drivers:' in the subject line.
This patch likely needs to moved to 4/7 since the last patch also
iterated over the list.
Tom
>
> Signed-off-by: Matthew Gerlach <matthew.gerlach@...ux.intel.com>
> Signed-off-by: Tianfei Zhang <tianfei.zhang@...el.com>
> ---
> drivers/fpga/dfl.c | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/drivers/fpga/dfl.c b/drivers/fpga/dfl.c
> index cfc539a656f0..a5263ac258c5 100644
> --- a/drivers/fpga/dfl.c
> +++ b/drivers/fpga/dfl.c
> @@ -1708,6 +1708,8 @@ int dfl_fpga_cdev_config_ports_vf(struct dfl_fpga_cdev *cdev, int num_vfs)
> int ret = 0, port_count = 0;
>
> mutex_lock(&cdev->lock);
> + if (list_empty(&cdev->port_dev_list))
> + goto done;
>
> list_for_each_entry(pdata, &cdev->port_dev_list, node) {
> if (pdata->dev)
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