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Message-ID: <YgwAHU7gCnik8Kv6@zn.tnic>
Date: Tue, 15 Feb 2022 20:33:49 +0100
From: Borislav Petkov <bp@...en8.de>
To: Pawan Gupta <pawan.kumar.gupta@...ux.intel.com>
Cc: Andrew Cooper <andrew.cooper3@...rix.com>,
Thomas Gleixner <tglx@...utronix.de>,
Ingo Molnar <mingo@...hat.com>,
Dave Hansen <dave.hansen@...ux.intel.com>, x86@...nel.org,
"H. Peter Anvin" <hpa@...or.com>, Andi Kleen <ak@...ux.intel.com>,
Tony Luck <tony.luck@...el.com>, linux-kernel@...r.kernel.org,
antonio.gomez.iglesias@...ux.intel.com, neelima.krishnan@...el.com,
stable@...r.kernel.org
Subject: Re: [PATCH] x86/tsx: Use MSR_TSX_CTRL to clear CPUID bits
On Tue, Feb 15, 2022 at 10:19:31AM -0800, Pawan Gupta wrote:
> I admit it has gotten complicated with so many bits associated with TSX.
Yah, and looka here:
https://github.com/andyhhp/xen/commit/ad9f7c3b2e0df38ad6d54f4769d4dccf765fbcee
It seems it isn't complicated enough. ;-\
Andy just made me aware of this thing where you guys have added a new
MSR bit:
MSR_MCU_OPT_CTRL[1] which is called something like
MCU_OPT_CTRL_RTM_ALLOW or so. And lemme quote from that patch:
/*
* Probe for the February 2022 microcode which de-features TSX on
* TAA-vulnerable client parts - WHL-R/CFL-R.
*
* RTM_ALWAYS_ABORT (read above) enumerates the new functionality,
* but is read as zero if MCU_OPT_CTRL.RTM_ALLOW has been set
* before we run. Undo this.
*/
so MCU_OPT_CTRL.RTM_ALLOW=1 would have
CPUID.X86_FEATURE_RTM_ALWAYS_ABORT=0, which means, we cannot tie TSX disabling on
X86_FEATURE_RTM_ALWAYS_ABORT only.
So this would need more work, it seems to me.
Thx.
--
Regards/Gruss,
Boris.
https://people.kernel.org/tglx/notes-about-netiquette
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