lists.openwall.net | lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC | |
Open Source and information security mailing list archives
| ||
|
Message-ID: <20220215124606.28627-1-bharat.kumar.gogada@xilinx.com> Date: Tue, 15 Feb 2022 18:16:04 +0530 From: Bharat Kumar Gogada <bharat.kumar.gogada@...inx.com> To: <linux-pci@...r.kernel.org>, <linux-kernel@...r.kernel.org> CC: <lorenzo.pieralisi@....com>, <bhelgaas@...gle.com>, <michals@...inx.com>, Bharat Kumar Gogada <bharat.kumar.gogada@...inx.com> Subject: [PATCH v2 0/2] Add support for Xilinx Versal CPM5 Root Port Xilinx Versal Premium series has CPM5 block which supports Root Port functioning at Gen5 speed. Xilinx Versal CPM5 has few changes with existing CPM block. - CPM5 has dedicated register space for control and status registers. - CPM5 legacy interrupt handling needs additonal register bit to enable and handle legacy interrupts. Changes in v2: - changed commit message. Bharat Kumar Gogada (2): dt-bindings: PCI: xilinx-cpm: Add Versal CPM5 Root Port PCI: xilinx-cpm: Add support for Versal CPM5 Root Port .../bindings/pci/xilinx-versal-cpm.yaml | 47 ++++++++++++++++--- drivers/pci/controller/pcie-xilinx-cpm.c | 33 ++++++++++++- 2 files changed, 72 insertions(+), 8 deletions(-) -- 2.17.1
Powered by blists - more mailing lists