linux-kernel - Re: [PATCH v11 0/3] Add basic SoC support for mediatek mt8195

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Message-ID: <e17592b2-5e02-44a6-5c21-ac599af5fce1@mediatek.com>
Date:   Thu, 17 Feb 2022 14:24:58 +0800
From:   Macpaul Lin <macpaul.lin@...iatek.com>
To:     Tinghan Shen <tinghan.shen@...iatek.com>,
        Rob Herring <robh+dt@...nel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski@...onical.com>,
        Linus Walleij <linus.walleij@...aro.org>,
        Matthias Brugger <matthias.bgg@...il.com>,
        AngeloGioacchino Del Regno 
        <angelogioacchino.delregno@...labora.com>,
        "Bartosz Golaszewski" <bgolaszewski@...libre.com>,
        Sean Wang <Sean.Wang@...iatek.com>
CC:     "devicetree@...r.kernel.org" <devicetree@...r.kernel.org>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
        "linux-gpio@...r.kernel.org" <linux-gpio@...r.kernel.org>,
        "linux-arm-kernel@...ts.infradead.org" 
        <linux-arm-kernel@...ts.infradead.org>,
        "linux-mediatek@...ts.infradead.org" 
        <linux-mediatek@...ts.infradead.org>,
        Project_Global_Chrome_Upstream_Group 
        <Project_Global_Chrome_Upstream_Group@...iatek.com>,
        "ryder.lee@...nel.org" <ryder.lee@...nel.org>,
        "wenst@...omium.org" <wenst@...omium.org>,
        Chunfeng Yun (云春峰) 
        <Chunfeng.Yun@...iatek.com>, Fabien Parent <fparent@...libre.com>,
        Bear Wang <bear.wang@...iatek.com>,
        Pablo Sun <pablo.sun@...iatek.com>
Subject: Re: [PATCH v11 0/3] Add basic SoC support for mediatek mt8195

On 2/16/22 7:31 PM, Tinghan Shen wrote:
> This series adds basic SoC support for Mediatek's SoC MT8195.
> 
> ---
> Changes in v11:
>    - rebase on 5.17-rc4
> Changes in v10:
>    - clean CC list
> Changes in v9:
>    - remove duplicated cpus dt-bindings patch in v8
> Changes in v8:
>    - v7 mediatek,spi-mtk-nor.yaml patch is applied in branch for-5.17 at
>      kernel/git/broonie/spi.git
>    - v7 pinctrl-mt8195.yaml patch is applied in branch for-next at
>      kernel/git/linusw/linux-pinctrl.git
>    - add cortex-a78 compatible to cpus dt-bindings
>    - add mediatek,drive-strength-adv property to pinctrl dt-bindings
>    - fix evb dts
>      - remove i2c nodes with disabled status from dts
>      - fix pin properties not match pinctrl dt-bindings
>      - remove unnecessary u3port*
>    - fix dtsi
>      - fix node format
>      - reorder oscillator* nodes
>      - fix node name of cpu idle nodes
>      - remove clock-frequency property in the timer node
>      - reorder clock and clock names in usb nodes
> Changes in v7:
>    - refine title of spi-nor dt-bindings patch
>    - refine commit message of pinctrl dt-bindings patch
>    - update pinctrl-mt8195.yaml
>      - change property pattern from 'pins' to '^pins'
>      - update examples with new property in descriptions
>      - add new example
>    - drop '_' from node names of pinctrl subnodes in mt8195-evb.dts
> Changes in v6:
>    - rebase on 5.16-rc1
>    - add new clock name to spi-nor dt-bindings
>    - add "pins" property in pinctrl dt-bindings
>    - fix fails of dtbs_checks
>      - remove "arm,armv8" not matched in yaml from cpu compatile
>      - fix node name of xhci
>      - remvoe xhci upstreaming wakeup properties
>      - remove xhci unused properties address-cells and size-cells
>      - fix node name of ufs-phy
>      - fix node name of spi-nor
>      - fix node name and sub-nodes of pinctrl
>      - fix mmc compatible
> Changes in v5:
>    - enable basic nodes in mt8195-evb.dts
>    - remove dedicated clock nodes
>    - add mmc2 node
>    - fix interrupt number of pinctrl node
>    - update clock nodes to apply internal fixes
>    - add dt-bindings for perficfg node
> 
> v4 thread:
> https://urldefense.com/v3/__https://lore.kernel.org/all/20210922093303.23720-2-seiya.wang@mediatek.com/__;!!CTRNKA9wMg0ARbw!xv2H7ZXYIUG7YY1R5OuFgbvDxyfaE6dkkD5H_PciKAZAb5jk-uThgSgItGuvt2d6gCs$
> v3 thread:
> https://urldefense.com/v3/__https://lore.kernel.org/all/20210601075350.31515-2-seiya.wang@mediatek.com/__;!!CTRNKA9wMg0ARbw!xv2H7ZXYIUG7YY1R5OuFgbvDxyfaE6dkkD5H_PciKAZAb5jk-uThgSgItGuvgIQSNYo$
> v2 thread:
> https://urldefense.com/v3/__https://lore.kernel.org/all/20210319023427.16711-10-seiya.wang@mediatek.com/__;!!CTRNKA9wMg0ARbw!xv2H7ZXYIUG7YY1R5OuFgbvDxyfaE6dkkD5H_PciKAZAb5jk-uThgSgItGuvBx50AeU$
> v1 thread:
> https://urldefense.com/v3/__https://lore.kernel.org/all/20210316111443.3332-11-seiya.wang@mediatek.com/__;!!CTRNKA9wMg0ARbw!xv2H7ZXYIUG7YY1R5OuFgbvDxyfaE6dkkD5H_PciKAZAb5jk-uThgSgItGuvpH_NtEY$
> ---
> 
> Tinghan Shen (3):
>    dt-bindings: arm: mediatek: Add mt8195 pericfg compatible
>    dt-bindings: pinctrl: mt8195: Add mediatek,drive-strength-adv property
>    arm64: dts: Add mediatek SoC mt8195 and evaluation board
> 
>   .../arm/mediatek/mediatek,pericfg.yaml        |    1 +
>   .../bindings/pinctrl/pinctrl-mt8195.yaml      |   35 +
>   arch/arm64/boot/dts/mediatek/Makefile         |    1 +
>   arch/arm64/boot/dts/mediatek/mt8195-evb.dts   |  161 +++
>   arch/arm64/boot/dts/mediatek/mt8195.dtsi      | 1049 +++++++++++++++++
>   5 files changed, 1247 insertions(+)
>   create mode 100644 arch/arm64/boot/dts/mediatek/mt8195-evb.dts
>   create mode 100644 arch/arm64/boot/dts/mediatek/mt8195.dtsi
> 

Just trying to clarify something.
Dear Tinghan, is there any "lines of code" changed between v10 and v11  
due to the rebase? Is that you just updated the parent commit hash for  
rebasing this patchset to 5.17-rc4? I've just get confused if v10 and  
v11 are duplicated then should we need to review the patch again in detail?

Thanks.
Macpaul Lin