linux-kernel - [PATCH 04/17] arm64: dts: mt8192: Add gce node

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Message-ID: <20220217134027.508-5-allen-kh.cheng@mediatek.com>
Date:   Thu, 17 Feb 2022 21:40:22 +0800
From:   Allen-KH Cheng <allen-kh.cheng@...iatek.com>
To:     Matthias Brugger <matthias.bgg@...il.com>,
        Rob Herring <robh+dt@...nel.org>,
        --to=Krzysztof Kozlowski <krzysztof.kozlowski@...onical.com>
CC:     <Project_Global_Chrome_Upstream_Group@...iatek.com>,
        <devicetree@...r.kernel.org>,
        <linux-arm-kernel@...ts.infradead.org>,
        <linux-kernel@...r.kernel.org>,
        <linux-mediatek@...ts.infradead.org>,
        "Chen-Yu Tsai" <wenst@...omium.org>,
        Ryder Lee <ryder.lee@...nel.org>,
        Allen-KH Cheng <allen-kh.cheng@...iatek.com>
Subject: [PATCH 04/17] arm64: dts: mt8192: Add gce node

Add gce node for mt8192 SoC.

Signed-off-by: Allen-KH Cheng <allen-kh.cheng@...iatek.com>
---
 arch/arm64/boot/dts/mediatek/mt8192.dtsi | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index 8635c8a53472..c432711a318d 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -552,6 +552,15 @@
 			#size-cells = <0>;
 		};
 
+		gce: mailbox@...28000 {
+			compatible = "mediatek,mt8192-gce";
+			reg = <0 0x10228000 0 0x4000>;
+			interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH 0>;
+			#mbox-cells = <3>;
+			clocks = <&infracfg CLK_INFRA_GCE>;
+			clock-names = "gce";
+		};
+
 		scp_adsp: clock-controller@...20000 {
 			compatible = "mediatek,mt8192-scp_adsp";
 			reg = <0 0x10720000 0 0x1000>;
-- 
2.18.0