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Message-Id: <20220218215549.4274-1-song.bao.hua@hisilicon.com>
Date:   Sat, 19 Feb 2022 05:55:49 +0800
From:   Barry Song <21cnbao@...il.com>
To:     maz@...nel.org, tglx@...utronix.de, will@...nel.org,
        linux-kernel@...r.kernel.org
Cc:     linux-arm-kernel@...ts.infradead.org, linuxarm@...wei.com,
        Barry Song <song.bao.hua@...ilicon.com>
Subject: [PATCH] irqchip/gic-v3: use dsb(ishst) to synchronize data to smp before issuing ipi

dsb(ishst) should be enough here as we only need to guarantee the
visibility of data to other CPUs in smp inner domain before we
send the ipi.

Signed-off-by: Barry Song <song.bao.hua@...ilicon.com>
---
 drivers/irqchip/irq-gic-v3.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/irqchip/irq-gic-v3.c b/drivers/irqchip/irq-gic-v3.c
index 5e935d97207d..0efe1a9a9f3b 100644
--- a/drivers/irqchip/irq-gic-v3.c
+++ b/drivers/irqchip/irq-gic-v3.c
@@ -1211,7 +1211,7 @@ static void gic_ipi_send_mask(struct irq_data *d, const struct cpumask *mask)
 	 * Ensure that stores to Normal memory are visible to the
 	 * other CPUs before issuing the IPI.
 	 */
-	wmb();
+	dsb(ishst);
 
 	for_each_cpu(cpu, mask) {
 		u64 cluster_id = MPIDR_TO_SGI_CLUSTER_ID(cpu_logical_map(cpu));
-- 
2.25.1

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