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Message-ID: <20220218091633.9368-6-allen-kh.cheng@mediatek.com>
Date: Fri, 18 Feb 2022 17:16:15 +0800
From: Allen-KH Cheng <allen-kh.cheng@...iatek.com>
To: Matthias Brugger <matthias.bgg@...il.com>,
Rob Herring <robh+dt@...nel.org>,
--to=Krzysztof Kozlowski <krzysztof.kozlowski@...onical.com>
CC: <Project_Global_Chrome_Upstream_Group@...iatek.com>,
<devicetree@...r.kernel.org>,
<linux-arm-kernel@...ts.infradead.org>,
<linux-kernel@...r.kernel.org>,
<linux-mediatek@...ts.infradead.org>,
"Chen-Yu Tsai" <wenst@...omium.org>,
Ryder Lee <ryder.lee@...nel.org>,
Allen-KH Cheng <allen-kh.cheng@...iatek.com>
Subject: [PATCH v2 05/23] arm64: dts: mt8192: Add SCP node
Add SCP node for mt8192 SoC.
Signed-off-by: Allen-KH Cheng <allen-kh.cheng@...iatek.com>
---
arch/arm64/boot/dts/mediatek/mt8192.dtsi | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index f92d8d7afa5d..61aadd7bd397 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -706,6 +706,18 @@
status = "disabled";
};
+ scp: scp@...00000 {
+ compatible = "mediatek,mt8192-scp";
+ reg = <0 0x10500000 0 0x100000>,
+ <0 0x10700000 0 0x8000>,
+ <0 0x10720000 0 0xe0000>;
+ reg-names = "sram", "l1tcm", "cfg";
+ interrupts = <GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&infracfg CLK_INFRA_SCPSYS>;
+ clock-names = "main";
+ status = "disabled";
+ };
+
nor_flash: spi@...34000 {
compatible = "mediatek,mt8192-nor";
reg = <0 0x11234000 0 0xe0>;
--
2.18.0
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