linux-kernel - Re: [PATCH v5 21/34] iommu/mediatek: Add PCIe support

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Message-ID: <81cd0888-b202-feae-1c54-99ad2ef3f8cb@collabora.com>
Date:   Fri, 18 Feb 2022 13:52:25 +0100
From:   AngeloGioacchino Del Regno 
        <angelogioacchino.delregno@...labora.com>
To:     Yong Wu <yong.wu@...iatek.com>, Joerg Roedel <joro@...tes.org>,
        Rob Herring <robh+dt@...nel.org>,
        Matthias Brugger <matthias.bgg@...il.com>,
        Will Deacon <will@...nel.org>
Cc:     Robin Murphy <robin.murphy@....com>,
        Krzysztof Kozlowski <krzysztof.kozlowski@...onical.com>,
        Tomasz Figa <tfiga@...omium.org>,
        linux-mediatek@...ts.infradead.org, srv_heupstream@...iatek.com,
        devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
        linux-arm-kernel@...ts.infradead.org,
        iommu@...ts.linux-foundation.org,
        Hsin-Yi Wang <hsinyi@...omium.org>, youlin.pei@...iatek.com,
        anan.sun@...iatek.com, xueqi.zhang@...iatek.com,
        yen-chang.chen@...iatek.com, mingyuan.ma@...iatek.com,
        yf.wang@...iatek.com, libo.kang@...iatek.com,
        chengci.xu@...iatek.com
Subject: Re: [PATCH v5 21/34] iommu/mediatek: Add PCIe support

Il 17/02/22 12:34, Yong Wu ha scritto:
> Currently the code for of_iommu_configure_dev_id is like this:
> 
> static int of_iommu_configure_dev_id(struct device_node *master_np,
>                                       struct device *dev,
>                                       const u32 *id)
> {
>         struct of_phandle_args iommu_spec = { .args_count = 1 };
> 
>         err = of_map_id(master_np, *id, "iommu-map",
>                         "iommu-map-mask", &iommu_spec.np,
>                         iommu_spec.args);
> ...
> }
> 
> It supports only one id output. BUT our PCIe HW has two ID(one is for
> writing, the other is for reading). I'm not sure if we should change
> of_map_id to support output MAX_PHANDLE_ARGS.
> 
> Here add the solution in ourselve drivers. If it's pcie case, enable one
> more bit.
> 
> Not all infra iommu support PCIe, thus add a PCIe support flag here.
> 
> Signed-off-by: Yong Wu <yong.wu@...iatek.com>

Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@...labora.com>