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Message-ID: <5ad1baeb-6744-1c60-08a8-063db0a2ad03@collabora.com>
Date: Fri, 18 Feb 2022 13:56:25 +0100
From: AngeloGioacchino Del Regno
<angelogioacchino.delregno@...labora.com>
To: Allen-KH Cheng <allen-kh.cheng@...iatek.com>,
Matthias Brugger <matthias.bgg@...il.com>,
Rob Herring <robh+dt@...nel.org>,
--to=Krzysztof Kozlowski <krzysztof.kozlowski@...onical.com>
Cc: Project_Global_Chrome_Upstream_Group@...iatek.com,
devicetree@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
linux-kernel@...r.kernel.org, linux-mediatek@...ts.infradead.org,
Chen-Yu Tsai <wenst@...omium.org>,
Ryder Lee <ryder.lee@...nel.org>,
Nícolas F. R. A. Prado
<nfraprado@...labora.com>
Subject: Re: [PATCH v2 22/23] arm64: dts: mt8192: Add gce info for display
nodes
Il 18/02/22 10:16, Allen-KH Cheng ha scritto:
> Add gce info for display nodes.
>
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@...iatek.com>
Please mention that this is required to get drivers' CMDQ support in this
commit message, as this is critical information.
> ---
> arch/arm64/boot/dts/mediatek/mt8192.dtsi | 16 ++++++++++++++++
> 1 file changed, 16 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> index 1f1555fd18f5..df884c48669e 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> @@ -1226,6 +1226,9 @@
> mmsys: syscon@...00000 {
> compatible = "mediatek,mt8192-mmsys", "syscon";
> reg = <0 0x14000000 0 0x1000>;
> + mboxes = <&gce 0 CMDQ_THR_PRIO_HIGHEST 1>,
> + <&gce 1 CMDQ_THR_PRIO_HIGHEST 1>;
> + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>;
> #clock-cells = <1>;
> };
>
> @@ -1234,6 +1237,8 @@
> reg = <0 0x14001000 0 0x1000>;
> interrupts = <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH 0>;
> clocks = <&mmsys CLK_MM_DISP_MUTEX0>;
> + mediatek,gce-events = <CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_0>,
> + <CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_1>;
> };
>
> smi_common: smi@...02000 {
> @@ -1275,6 +1280,7 @@
> iommus = <&iommu0 M4U_PORT_L0_OVL_RDMA0>,
> <&iommu0 M4U_PORT_L0_OVL_RDMA0_HDR>;
> power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
> + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x5000 0x1000>;
> };
>
> ovl_2l0: ovl@...06000 {
> @@ -1285,6 +1291,7 @@
> clocks = <&mmsys CLK_MM_DISP_OVL0_2L>;
> iommus = <&iommu0 M4U_PORT_L1_OVL_2L_RDMA0>,
> <&iommu0 M4U_PORT_L1_OVL_2L_RDMA0_HDR>;
> + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x6000 0x1000>;
> };
>
> rdma0: rdma@...07000 {
> @@ -1296,6 +1303,7 @@
> mediatek,larb = <&larb0>;
> mediatek,rdma-fifo-size = <5120>;
> power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
> + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x7000 0x1000>;
> };
>
> color0: color@...09000 {
> @@ -1305,6 +1313,7 @@
> interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH 0>;
> power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
> clocks = <&mmsys CLK_MM_DISP_COLOR0>;
> + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x9000 0x1000>;
> };
>
> ccorr0: ccorr@...0a000 {
> @@ -1313,6 +1322,7 @@
> interrupts = <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH 0>;
> power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
> clocks = <&mmsys CLK_MM_DISP_CCORR0>;
> + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xa000 0x1000>;
> };
>
> aal0: aal@...0b000 {
> @@ -1321,6 +1331,7 @@
> interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH 0>;
> power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
> clocks = <&mmsys CLK_MM_DISP_AAL0>;
> + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xb000 0x1000>;
> };
>
> gamma0: gamma@...0c000 {
> @@ -1330,6 +1341,7 @@
> interrupts = <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH 0>;
> power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
> clocks = <&mmsys CLK_MM_DISP_GAMMA0>;
> + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xc000 0x1000>;
> };
>
> postmask0: postmask@...0d000 {
> @@ -1339,6 +1351,7 @@
> power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
> clocks = <&mmsys CLK_MM_DISP_POSTMASK0>;
> iommus = <&iommu0 M4U_PORT_L0_DISP_POSTMASK0>;
> + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xd000 0x1000>;
> };
>
> dither0: dither@...0e000 {
> @@ -1348,6 +1361,7 @@
> interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH 0>;
> power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
> clocks = <&mmsys CLK_MM_DISP_DITHER0>;
> + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xe000 0x1000>;
> };
>
> dsi0: dsi@...10000 {
> @@ -1371,6 +1385,7 @@
> clocks = <&mmsys CLK_MM_DISP_OVL2_2L>;
> iommus = <&iommu0 M4U_PORT_L1_OVL_2L_RDMA2>,
> <&iommu0 M4U_PORT_L1_OVL_2L_RDMA2_HDR>;
> + mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x4000 0x1000>;
> };
>
> rdma4: rdma@...15000 {
> @@ -1381,6 +1396,7 @@
> clocks = <&mmsys CLK_MM_DISP_RDMA4>;
> iommus = <&iommu0 M4U_PORT_L1_DISP_RDMA4>;
> mediatek,rdma-fifo-size = <2048>;
> + mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x5000 0x1000>;
> };
>
> dpi0: dpi@...16000 {
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