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Message-ID: <202202201931.p5hX32R7-lkp@intel.com>
Date: Sun, 20 Feb 2022 19:38:18 +0800
From: kernel test robot <lkp@...el.com>
To: Atish Patra <atish.patra@....com>
Cc: kbuild-all@...ts.01.org, Atish Patra <Atish.Patra@....com>,
linux-kernel@...r.kernel.org, linux-doc@...r.kernel.org
Subject: [atishp04:sbi_pmu_v6 15/17] drivers/perf/riscv_pmu_sbi.c:498:
warning: This comment starts with '/**', but isn't a kernel-doc comment.
Refer Documentation/doc-guide/kernel-doc.rst
tree: https://github.com/atishp04/linux sbi_pmu_v6
head: 876094386d4f915d81ec2ee5b8b412987a10d808
commit: 4d77ea7126a3073504f29575eacacc63547fb579 [15/17] RISC-V: Add sscofpmf extension support
config: riscv-allyesconfig (https://download.01.org/0day-ci/archive/20220220/202202201931.p5hX32R7-lkp@intel.com/config)
compiler: riscv64-linux-gcc (GCC) 11.2.0
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# https://github.com/atishp04/linux/commit/4d77ea7126a3073504f29575eacacc63547fb579
git remote add atishp04 https://github.com/atishp04/linux
git fetch --no-tags atishp04 sbi_pmu_v6
git checkout 4d77ea7126a3073504f29575eacacc63547fb579
# save the config file to linux build tree
mkdir build_dir
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-11.2.0 make.cross O=build_dir ARCH=riscv SHELL=/bin/bash drivers/perf/
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@...el.com>
All warnings (new ones prefixed by >>):
drivers/perf/riscv_pmu_sbi.c:42: warning: cannot understand function prototype: 'union sbi_pmu_ctr_info *pmu_ctr_list; '
>> drivers/perf/riscv_pmu_sbi.c:498: warning: This comment starts with '/**', but isn't a kernel-doc comment. Refer Documentation/doc-guide/kernel-doc.rst
* This function starts all the used counters in two step approach.
vim +498 drivers/perf/riscv_pmu_sbi.c
496
497 /**
> 498 * This function starts all the used counters in two step approach.
499 * Any counter that did not overflow can be start in a single step
500 * while the overflowed counters need to be started with updated initialization
501 * value.
502 */
503 static inline void pmu_sbi_start_overflow_mask(struct riscv_pmu *pmu,
504 unsigned long ctr_ovf_mask)
505 {
506 int idx = 0;
507 struct cpu_hw_events *cpu_hw_evt = this_cpu_ptr(pmu->hw_events);
508 struct perf_event *event;
509 unsigned long flag = SBI_PMU_START_FLAG_SET_INIT_VALUE;
510 unsigned long ctr_start_mask = 0;
511 uint64_t max_period;
512 struct hw_perf_event *hwc;
513 u64 init_val = 0;
514
515 ctr_start_mask = cpu_hw_evt->used_hw_ctrs[0] & ~ctr_ovf_mask;
516
517 /* Start all the counters that did not overflow in a single shot */
518 sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_START, 0, ctr_start_mask,
519 0, 0, 0, 0);
520
521 /* Reinitialize and start all the counter that overflowed */
522 while (ctr_ovf_mask) {
523 if (ctr_ovf_mask & 0x01) {
524 event = cpu_hw_evt->events[idx];
525 hwc = &event->hw;
526 max_period = riscv_pmu_ctr_get_width_mask(event);
527 init_val = local64_read(&hwc->prev_count) & max_period;
528 sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_START, idx, 1,
529 flag, init_val, 0, 0);
530 }
531 ctr_ovf_mask = ctr_ovf_mask >> 1;
532 idx++;
533 }
534 }
535
---
0-DAY CI Kernel Test Service, Intel Corporation
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