linux-kernel - Re: [PATCH v2 2/6] irqchip/riscv-intc: Create domain using named fwnode

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [day] [month] [year] [list]

Date:   Mon, 21 Feb 2022 15:14:01 +0530
From:   Anup Patel <anup@...infault.org>
To:     Marc Zyngier <maz@...nel.org>
Cc:     Jessica Clarke <jrtc27@...c27.com>,
        Anup Patel <apatel@...tanamicro.com>,
        Palmer Dabbelt <palmer@...belt.com>,
        Paul Walmsley <paul.walmsley@...ive.com>,
        Thomas Gleixner <tglx@...utronix.de>,
        Daniel Lezcano <daniel.lezcano@...aro.org>,
        Atish Patra <atishp@...shpatra.org>,
        Alistair Francis <Alistair.Francis@....com>,
        linux-riscv <linux-riscv@...ts.infradead.org>,
        "linux-kernel@...r.kernel.org List" <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH v2 2/6] irqchip/riscv-intc: Create domain using named fwnode

On Mon, Feb 21, 2022 at 2:55 PM Marc Zyngier <maz@...nel.org> wrote:
>
> On Sat, 19 Feb 2022 14:51:22 +0000,
> Jessica Clarke <jrtc27@...c27.com> wrote:
> >
> > On 19 Feb 2022, at 09:32, Marc Zyngier <maz@...nel.org> wrote:
> > >
> > > But how do you plan to work around the fact that everything is currently
> > > build around having a node (and an irqdomain) per CPU? The PLIC, for example,
> > > clearly has one parent per CPU, not one global parent.
> > >
> > > I'm sure there was a good reason for this, and I suspect merging the domains
> > > will simply end up breaking things.
> >
> > On the contrary, the drivers rely on the controller being the same
> > across all harts, with riscv_intc_init skipping initialisation for all
> > but the boot hart’s controller. The bindings are a complete pain to
> > deal with as a result, what you *want* is like you have in the Arm
> > world where there is just one interrupt controller in the device tree
> > with some of the interrupts per-processor, but instead we have this
> > overengineered nuisance. The only reason there are per-hart interrupt
> > controllers is because that’s how the contexts for the CLINT/PLIC are
> > specified, but that really should have been done another way rather
> > than abusing the interrupts-extended property for that. In the FreeBSD
> > world we’ve been totally ignoring the device tree nodes for the local
> > interrupt controllers but for my AIA and ACLINT branch I started a few
> > months ago (though ACLINT's now been completely screwed up by RVI
> > politics, things have been renamed and split up differently in the past
> > few days and software interrupts de-prioritised with no current path to
> > ratification, so that was a waste of my time) I just hang the driver
> > off the boot hart’s node and leave all the others as totally ignored
> > and a waste of space other than to figure out the contexts for the PLIC
> > etc.
> >
> > TL;DR yes the bindings are awful, no there’s no issue with merging the
> > domains.
>
> I don't know how that flies with something like[1], where CPU0 only
> gets interrupts in M-Mode and not S-Mode. Maybe it doesn't really
> matter, but this sort of asymmetric routing is totally backward.

The example PLIC DT node which I provided is from SiFive FU540, where
we have 5 CPUs. The CPU0 in FU540 is a cache-coherent microcontroller
having only M-mode (i.e. No MMU hence not Linux capable).

>
> It sometime feels like the RV folks are actively trying to make this
> architecture a mess... :-/

Well, I still fail to understand what is messy here.

Regards,
Anup

>
>         M.
>
> [1] CAAhSdy0jTTDzoc+3T_8uLiWfBN3AFCWj99Ayc-Yh8FBfzUY2sQ@...l.gmail.com
>
> --
> Without deviation from the norm, progress is not possible.