linux-kernel - arch/mips/mm/tlbex.c:2173 build_r4000_tlb_load

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Message-ID: <202202212221.MSvbhv1n-lkp@intel.com>
Date:   Mon, 21 Feb 2022 22:09:13 +0800
From:   kernel test robot <lkp@...el.com>
To:     "Gustavo A. R. Silva" <gustavoars@...nel.org>
Cc:     kbuild-all@...ts.01.org, linux-kernel@...r.kernel.org
Subject: arch/mips/mm/tlbex.c:2173 build_r4000_tlb_load_handler() warn:
 inconsistent indenting

tree:   https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git master
head:   cfb92440ee71adcc2105b0890bb01ac3cddb8507
commit: bc431d2153cc290573531601b5004babe7011568 MIPS: Fix fall-through warnings for Clang
date:   7 months ago
config: mips-randconfig-m031-20220221 (https://download.01.org/0day-ci/archive/20220221/202202212221.MSvbhv1n-lkp@intel.com/config)
compiler: mipsel-linux-gcc (GCC) 11.2.0

If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@...el.com>

New smatch warnings:
arch/mips/mm/tlbex.c:2173 build_r4000_tlb_load_handler() warn: inconsistent indenting

Old smatch warnings:
arch/mips/mm/tlbex.c:1744 iPTE_SW() warn: inconsistent indenting
arch/mips/mm/tlbex.c:2603 check_pabits() warn: always true condition '(fillbits >= ((__builtin_constant_p(0)) ?(((0) < 2) ?0:63 - __builtin_clzll(0)):((4 <= 4)) ?__ilog2_u32(0):__ilog2_u64(0))) => (0-u32max >= 0)'

vim +2173 arch/mips/mm/tlbex.c

  2114	
  2115	static void build_r4000_tlb_load_handler(void)
  2116	{
  2117		u32 *p = (u32 *)msk_isa16_mode((ulong)handle_tlbl);
  2118		struct uasm_label *l = labels;
  2119		struct uasm_reloc *r = relocs;
  2120		struct work_registers wr;
  2121	
  2122		memset(p, 0, handle_tlbl_end - (char *)p);
  2123		memset(labels, 0, sizeof(labels));
  2124		memset(relocs, 0, sizeof(relocs));
  2125	
  2126		if (bcm1250_m3_war()) {
  2127			unsigned int segbits = 44;
  2128	
  2129			uasm_i_dmfc0(&p, K0, C0_BADVADDR);
  2130			uasm_i_dmfc0(&p, K1, C0_ENTRYHI);
  2131			uasm_i_xor(&p, K0, K0, K1);
  2132			uasm_i_dsrl_safe(&p, K1, K0, 62);
  2133			uasm_i_dsrl_safe(&p, K0, K0, 12 + 1);
  2134			uasm_i_dsll_safe(&p, K0, K0, 64 + 12 + 1 - segbits);
  2135			uasm_i_or(&p, K0, K0, K1);
  2136			uasm_il_bnez(&p, &r, K0, label_leave);
  2137			/* No need for uasm_i_nop */
  2138		}
  2139	
  2140		wr = build_r4000_tlbchange_handler_head(&p, &l, &r);
  2141		build_pte_present(&p, &r, wr.r1, wr.r2, wr.r3, label_nopage_tlbl);
  2142		if (m4kc_tlbp_war())
  2143			build_tlb_probe_entry(&p);
  2144	
  2145		if (cpu_has_rixi && !cpu_has_rixiex) {
  2146			/*
  2147			 * If the page is not _PAGE_VALID, RI or XI could not
  2148			 * have triggered it.  Skip the expensive test..
  2149			 */
  2150			if (use_bbit_insns()) {
  2151				uasm_il_bbit0(&p, &r, wr.r1, ilog2(_PAGE_VALID),
  2152					      label_tlbl_goaround1);
  2153			} else {
  2154				uasm_i_andi(&p, wr.r3, wr.r1, _PAGE_VALID);
  2155				uasm_il_beqz(&p, &r, wr.r3, label_tlbl_goaround1);
  2156			}
  2157			uasm_i_nop(&p);
  2158	
  2159			/*
  2160			 * Warn if something may race with us & replace the TLB entry
  2161			 * before we read it here. Everything with such races should
  2162			 * also have dedicated RiXi exception handlers, so this
  2163			 * shouldn't be hit.
  2164			 */
  2165			WARN(cpu_has_tlbex_tlbp_race(), "Unhandled race in RiXi path");
  2166	
  2167			uasm_i_tlbr(&p);
  2168	
  2169			switch (current_cpu_type()) {
  2170			default:
  2171				if (cpu_has_mips_r2_exec_hazard) {
  2172					uasm_i_ehb(&p);
> 2173				fallthrough;
  2174	
  2175			case CPU_CAVIUM_OCTEON:
  2176			case CPU_CAVIUM_OCTEON_PLUS:
  2177			case CPU_CAVIUM_OCTEON2:
  2178					break;
  2179				}
  2180			}
  2181	
  2182			/* Examine  entrylo 0 or 1 based on ptr. */
  2183			if (use_bbit_insns()) {
  2184				uasm_i_bbit0(&p, wr.r2, ilog2(sizeof(pte_t)), 8);
  2185			} else {
  2186				uasm_i_andi(&p, wr.r3, wr.r2, sizeof(pte_t));
  2187				uasm_i_beqz(&p, wr.r3, 8);
  2188			}
  2189			/* load it in the delay slot*/
  2190			UASM_i_MFC0(&p, wr.r3, C0_ENTRYLO0);
  2191			/* load it if ptr is odd */
  2192			UASM_i_MFC0(&p, wr.r3, C0_ENTRYLO1);
  2193			/*
  2194			 * If the entryLo (now in wr.r3) is valid (bit 1), RI or
  2195			 * XI must have triggered it.
  2196			 */
  2197			if (use_bbit_insns()) {
  2198				uasm_il_bbit1(&p, &r, wr.r3, 1, label_nopage_tlbl);
  2199				uasm_i_nop(&p);
  2200				uasm_l_tlbl_goaround1(&l, p);
  2201			} else {
  2202				uasm_i_andi(&p, wr.r3, wr.r3, 2);
  2203				uasm_il_bnez(&p, &r, wr.r3, label_nopage_tlbl);
  2204				uasm_i_nop(&p);
  2205			}
  2206			uasm_l_tlbl_goaround1(&l, p);
  2207		}
  2208		build_make_valid(&p, &r, wr.r1, wr.r2, wr.r3);
  2209		build_r4000_tlbchange_handler_tail(&p, &l, &r, wr.r1, wr.r2);
  2210	

---
0-DAY CI Kernel Test Service, Intel Corporation
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