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Message-Id: <20220221131037.8809-10-srinivas.kandagatla@linaro.org>
Date: Mon, 21 Feb 2022 13:10:36 +0000
From: Srinivas Kandagatla <srinivas.kandagatla@...aro.org>
To: broonie@...nel.org
Cc: lgirdwood@...il.com, perex@...ex.cz, tiwai@...e.com,
pierre-louis.bossart@...ux.intel.com, alsa-devel@...a-project.org,
linux-kernel@...r.kernel.org, quic_srivasam@...cinc.com,
Srinivas Kandagatla <srinivas.kandagatla@...aro.org>
Subject: [PATCH 09/10] ASoC: codecs: tx-macro: setup soundwire clks correctly
For SoundWire Frame sync to be generated correctly we need both MCLK
and MCLKx2 (npl). Without pm runtime enabled these two clocks will remain on,
however after adding pm runtime support its possible that NPl clock could be
turned off even when SoundWire controller is active.
Fix this by enabling mclk and npl clk when SoundWire clks are enabled.
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@...aro.org>
---
sound/soc/codecs/lpass-tx-macro.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/sound/soc/codecs/lpass-tx-macro.c b/sound/soc/codecs/lpass-tx-macro.c
index 1c0f0d27ed42..f90786100d1a 100644
--- a/sound/soc/codecs/lpass-tx-macro.c
+++ b/sound/soc/codecs/lpass-tx-macro.c
@@ -1687,6 +1687,7 @@ static int swclk_gate_enable(struct clk_hw *hw)
struct tx_macro *tx = to_tx_macro(hw);
struct regmap *regmap = tx->regmap;
+ clk_prepare_enable(tx->clks[2].clk);
tx_macro_mclk_enable(tx, true);
if (tx->reset_swr)
regmap_update_bits(regmap, CDC_TX_CLK_RST_CTRL_SWR_CONTROL,
@@ -1713,6 +1714,7 @@ static void swclk_gate_disable(struct clk_hw *hw)
CDC_TX_SWR_CLK_EN_MASK, 0x0);
tx_macro_mclk_enable(tx, false);
+ clk_disable_unprepare(tx->clks[2].clk);
}
static int swclk_gate_is_enabled(struct clk_hw *hw)
@@ -1750,7 +1752,7 @@ static struct clk *tx_macro_register_mclk_output(struct tx_macro *tx)
struct clk_init_data init;
int ret;
- parent_clk_name = __clk_get_name(tx->clks[2].clk);
+ parent_clk_name = __clk_get_name(tx->clks[3].clk);
init.name = clk_name;
init.ops = &swclk_gate_ops;
--
2.21.0
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