lists.openwall.net | lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC | |
Open Source and information security mailing list archives
| ||
|
Message-ID: <2e40f311-d04a-899b-acef-a8194006d8cf@gmail.com> Date: Mon, 21 Feb 2022 16:40:56 +0900 From: Takahiro Kuwano <tkuw584924@...il.com> To: Tudor Ambarus <tudor.ambarus@...rochip.com>, p.yadav@...com, michael@...le.cc, Takahiro.Kuwano@...ineon.com Cc: miquel.raynal@...tlin.com, richard@....at, vigneshr@...com, linux-mtd@...ts.infradead.org, linux-kernel@...r.kernel.org, nicolas.ferre@...rochip.com, zhengxunli@...c.com.tw, jaimeliao@...c.com.tw, Bacem.Daassi@...ineon.com Subject: Re: [PATCH 1/3] mtd: spi-nor: core: Add helpers to read/write any register On 2/10/2022 11:33 AM, Tudor Ambarus wrote: > There are manufacturers that use registers indexed by address. Some of > them support "read/write any register" opcodes. Provide core methods that > can be used by all manufacturers. SPI NOR controller ops are intentionally > not supported as we intend to move all the SPI NOR controller drivers > under the SPI subsystem. > > Signed-off-by: Tudor Ambarus <tudor.ambarus@...rochip.com> > --- > drivers/mtd/spi-nor/core.c | 41 ++++++++++++++++++++++++++++++++++++++ > drivers/mtd/spi-nor/core.h | 4 ++++ > 2 files changed, 45 insertions(+) > > diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c > index 7d5e3acb0ae7..d394179689e6 100644 > --- a/drivers/mtd/spi-nor/core.c > +++ b/drivers/mtd/spi-nor/core.c > @@ -307,6 +307,47 @@ ssize_t spi_nor_write_data(struct spi_nor *nor, loff_t to, size_t len, > return nor->controller_ops->write(nor, to, len, buf); > } > > +/** > + * spi_nor_read_reg() - read register to flash memory > + * @nor: pointer to 'struct spi_nor'. > + * @op: SPI memory operation. op->data.buf must be DMA-able. > + * @proto: SPI protocol to use for the register operation. > + * > + * Return: zero on success, -errno otherwise > + */ > +int spi_nor_read_reg(struct spi_nor *nor, struct spi_mem_op *op, > + enum spi_nor_protocol proto) > +{ > + if (!nor->spimem) > + return -EOPNOTSUPP; > + > + spi_nor_spimem_setup_op(nor, op, proto); > + return spi_nor_spimem_exec_op(nor, op); > +} > + > +/** > + * spi_nor_write_reg() - write register to flash memory > + * @nor: pointer to 'struct spi_nor' > + * @op: SPI memory operation. op->data.buf must be DMA-able. > + * @proto: SPI protocol to use for the register operation. > + * > + * Return: zero on success, -errno otherwise > + */ > +int spi_nor_write_reg(struct spi_nor *nor, struct spi_mem_op *op, > + enum spi_nor_protocol proto) > +{ > + int ret; > + > + if (!nor->spimem) > + return -EOPNOTSUPP; > + > + ret = spi_nor_write_enable(nor); > + if (ret) > + return ret; > + spi_nor_spimem_setup_op(nor, op, proto); > + return spi_nor_spimem_exec_op(nor, op); > +} > + > /** > * spi_nor_write_enable() - Set write enable latch with Write Enable command. > * @nor: pointer to 'struct spi_nor'. > diff --git a/drivers/mtd/spi-nor/core.h b/drivers/mtd/spi-nor/core.h > index cbfb4fa7647f..c728454b5424 100644 > --- a/drivers/mtd/spi-nor/core.h > +++ b/drivers/mtd/spi-nor/core.h > @@ -578,6 +578,10 @@ ssize_t spi_nor_read_data(struct spi_nor *nor, loff_t from, size_t len, > u8 *buf); > ssize_t spi_nor_write_data(struct spi_nor *nor, loff_t to, size_t len, > const u8 *buf); > +int spi_nor_read_reg(struct spi_nor *nor, struct spi_mem_op *op, > + enum spi_nor_protocol proto); > +int spi_nor_write_reg(struct spi_nor *nor, struct spi_mem_op *op, > + enum spi_nor_protocol proto); > int spi_nor_erase_sector(struct spi_nor *nor, u32 addr); > > int spi_nor_otp_read_secr(struct spi_nor *nor, loff_t addr, size_t len, u8 *buf); Thank you for introducing these helpers. I revised my S25HL/HS-T series on top of this and confirmed that is working correctly. Tested-By: Takahiro Kuwano <Takahiro.Kuwano@...ineon.com> Best Regards, Takahiro
Powered by blists - more mailing lists