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Message-ID: <6874fd181ad46cd48f12da6ff5c955a64e193564.camel@intel.com>
Date: Tue, 22 Feb 2022 04:38:22 +0000
From: "Edgecombe, Rick P" <rick.p.edgecombe@...el.com>
To: "Poimboe, Josh" <jpoimboe@...hat.com>,
"peterz@...radead.org" <peterz@...radead.org>,
"hjl.tools@...il.com" <hjl.tools@...il.com>,
"x86@...nel.org" <x86@...nel.org>,
"joao@...rdrivepizza.com" <joao@...rdrivepizza.com>,
"Cooper, Andrew" <andrew.cooper3@...rix.com>
CC: "keescook@...omium.org" <keescook@...omium.org>,
"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
"mark.rutland@....com" <mark.rutland@....com>,
"samitolvanen@...gle.com" <samitolvanen@...gle.com>,
"ndesaulniers@...gle.com" <ndesaulniers@...gle.com>,
"Milburn, Alyssa" <alyssa.milburn@...el.com>
Subject: Re: [PATCH 14/29] x86/ibt: Add IBT feature, MSR and #CP handling
On Fri, 2022-02-18 at 17:49 +0100, Peter Zijlstra wrote:
> + cr4_set_bits(X86_CR4_CET);
> +
> + rdmsrl(MSR_IA32_S_CET, msr);
> + if (cpu_feature_enabled(X86_FEATURE_IBT))
> + msr |= CET_ENDBR_EN;
> + wrmsrl(MSR_IA32_S_CET, msr);
So I guess implicit in all of this is that MSR_IA32_S_CET will not be
managed by xsaves (makes sense).
But it still might be good to add the supervisor cet xfeature number to
XFEATURE_MASK_SUPERVISOR_UNSUPPORTED, with analogous reasoning to
XFEATURE_MASK_PT.
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