linux-kernel - Re: [PATCH v2 20/23] arm64: dts: mt8192: Add display nodes

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Date:   Wed, 23 Feb 2022 10:35:44 -0500
From:   Nícolas F. R. A. Prado 
        <nfraprado@...labora.com>
To:     Chen-Yu Tsai <wenst@...omium.org>
Cc:     Allen-KH Cheng <allen-kh.cheng@...iatek.com>,
        Matthias Brugger <matthias.bgg@...il.com>,
        Rob Herring <robh+dt@...nel.org>,
        --to=Krzysztof Kozlowski <krzysztof.kozlowski@...onical.com>,
        Project_Global_Chrome_Upstream_Group@...iatek.com,
        devicetree@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
        linux-kernel@...r.kernel.org, linux-mediatek@...ts.infradead.org,
        Ryder Lee <ryder.lee@...nel.org>
Subject: Re: [PATCH v2 20/23] arm64: dts: mt8192: Add display nodes

On Tue, Feb 22, 2022 at 06:24:29PM +0800, Chen-Yu Tsai wrote:
> Hi,
> 
> On Fri, Feb 18, 2022 at 5:16 PM Allen-KH Cheng
> <allen-kh.cheng@...iatek.com> wrote:
> >
> > Add display nodes for mt8192 SoC.
> >
> > Signed-off-by: Allen-KH Cheng <allen-kh.cheng@...iatek.com>
> > ---
> >  arch/arm64/boot/dts/mediatek/mt8192.dtsi | 115 +++++++++++++++++++++++
> >  1 file changed, 115 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > index e3314cdc7c1a..026f2d8141b0 100644
> > --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > @@ -32,6 +32,11 @@
> >                 i2c7 = &i2c7;
> >                 i2c8 = &i2c8;
> >                 i2c9 = &i2c9;
> > +               ovl0 = &ovl0;
> > +               ovl-2l0 = &ovl_2l0;
> > +               ovl-2l2 = &ovl_2l2;
> > +               rdma0 = &rdma0;
> > +               rdma4 = &rdma4;
> >         };
> >
> >         clk26m: oscillator0 {
> > @@ -1224,6 +1229,13 @@
> >                         #clock-cells = <1>;
> >                 };
> >
> > +               mutex: mutex@...01000 {
> > +                       compatible = "mediatek,mt8192-disp-mutex";
> > +                       reg = <0 0x14001000 0 0x1000>;
> > +                       interrupts = <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH 0>;
> > +                       clocks = <&mmsys CLK_MM_DISP_MUTEX0>;
> > +               };
> > +
> >                 smi_common: smi@...02000 {
> >                         compatible = "mediatek,mt8192-smi-common";
> >                         reg = <0 0x14002000 0 0x1000>;
> > @@ -1255,6 +1267,109 @@
> >                         power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
> >                 };
> >
> > +               ovl0: ovl@...05000 {
> > +                       compatible = "mediatek,mt8192-disp-ovl";
> > +                       reg = <0 0x14005000 0 0x1000>;
> > +                       interrupts = <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH 0>;
> > +                       clocks = <&mmsys CLK_MM_DISP_OVL0>;
> > +                       iommus = <&iommu0 M4U_PORT_L0_OVL_RDMA0>,
> > +                                <&iommu0 M4U_PORT_L0_OVL_RDMA0_HDR>;
> > +                       power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
> > +               };
> > +
> > +               ovl_2l0: ovl@...06000 {
> > +                       compatible = "mediatek,mt8192-disp-ovl-2l";
> > +                       reg = <0 0x14006000 0 0x1000>;
> > +                       interrupts = <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH 0>;
> > +                       power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
> > +                       clocks = <&mmsys CLK_MM_DISP_OVL0_2L>;
> > +                       iommus = <&iommu0 M4U_PORT_L1_OVL_2L_RDMA0>,
> > +                                <&iommu0 M4U_PORT_L1_OVL_2L_RDMA0_HDR>;
> > +               };
> > +
> > +               rdma0: rdma@...07000 {
> > +                       compatible = "mediatek,mt8192-disp-rdma";
> > +                       reg = <0 0x14007000 0 0x1000>;
> > +                       interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH 0>;
> > +                       clocks = <&mmsys CLK_MM_DISP_RDMA0>;
> > +                       iommus = <&iommu0 M4U_PORT_L0_DISP_RDMA0>;
> > +                       mediatek,larb = <&larb0>;
> > +                       mediatek,rdma-fifo-size = <5120>;
> > +                       power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
> > +               };
> > +
> > +               color0: color@...09000 {
> > +                       compatible = "mediatek,mt8192-disp-color",
> > +                                    "mediatek,mt8173-disp-color";
> > +                       reg = <0 0x14009000 0 0x1000>;
> > +                       interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH 0>;
> > +                       power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
> > +                       clocks = <&mmsys CLK_MM_DISP_COLOR0>;
> > +               };
> > +
> > +               ccorr0: ccorr@...0a000 {
> > +                       compatible = "mediatek,mt8192-disp-ccorr";
> > +                       reg = <0 0x1400a000 0 0x1000>;
> > +                       interrupts = <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH 0>;
> > +                       power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
> > +                       clocks = <&mmsys CLK_MM_DISP_CCORR0>;
> > +               };
> > +
> > +               aal0: aal@...0b000 {
> > +                       compatible = "mediatek,mt8192-disp-aal";
> 
> git.kernel.org/chunkuang.hu/c/4ed545e7d10049b5492afc184e61a67e478a2cfd
> 
> suggests that there should be a fallback compatible? Otherwise this
> doesn't probe.

Indeed, the "mediatek,mt8173-disp-aal" compatible should be appended here for
the node to probe.

Thanks,
Nícolas