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Message-ID: <20220223174014.GA139367@bhelgaas>
Date: Wed, 23 Feb 2022 11:40:14 -0600
From: Bjorn Helgaas <helgaas@...nel.org>
To: Richard Zhu <hongxing.zhu@....com>
Cc: l.stach@...gutronix.de, bhelgaas@...gle.com, broonie@...nel.org,
lorenzo.pieralisi@....com, jingoohan1@...il.com,
festevam@...il.com, francesco.dolcini@...adex.com,
linux-pci@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
linux-kernel@...r.kernel.org, kernel@...gutronix.de,
linux-imx@....com
Subject: Re: [PATCH v7 8/8] PCI: imx6: Add the compliance tests mode support
In subject:
s/Add the/Add/
On Wed, Feb 16, 2022 at 02:21:03PM +0800, Richard Zhu wrote:
> Refer to the system board signal Quality of PCIe archiecture PHY test
> specification. Signal quality tests(for example: jitters, differential
> eye opening and so on ) can be executed with devices in the
> polling.compliance state.
s/archiecture/architecture/
s/tests(for/tests (for/
s/jitters, /jitter, / (remove double space)
s/so on )/so on)/
Is this a reference to a spec? If so, I can't tell the name of the
spec, the revision, or the section number.
> To let the device support polling.compliance stat, the clocks and powers
> shouldn't be turned off when the probe of device driver is failed.
s/stat/state/
s/powers/power/
s/driver is failed/driver fails/
> Based on CLB(Compliance Load Board) Test Fixture and so on test
> equipments, the PHY link would be down during the compliance tests.
> Refer to this scenario, add the i.MX PCIe compliance tests mode enable
> support, and keep the clocks and powers on, and finish the driver probe
> without error return.
s/CLB(Compliance/CLB (Compliance/
> Use the "pci_imx6.compliance=1" in kernel command line to enable the
> compliance tests mode.
Thanks for including this in the commit log!
> ret = dw_pcie_host_init(&pci->pp);
> - if (ret < 0)
> + if (ret < 0) {
> + if (imx6_pcie_cmp_mode) {
> + dev_info(dev, "Driver loaded with compliance test mode enabled.\n");
To match other messages:
s/Driver loaded/driver loaded/
s/enabled./enabled/
> + ret = 0;
> + } else {
> + dev_err(dev, "Unable to add pcie port.\n");
s/Unable/unable/
s/pcie/PCIe/
s/port./port/
> + }
> return ret;
> + }
>
> if (pci_msi_enabled()) {
> u8 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_MSI);
> --
> 2.25.1
>
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