linux-kernel - Re: [PATCH 4/6] PCI: qcom: Add SM8150 SoC support

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Message-ID: <CAA8EJppDVo5rN3swiVoE8zAqCTmwQD9RZAxbrP0CPO30kQTBmA@mail.gmail.com>
Date:   Thu, 24 Feb 2022 00:51:23 +0300
From:   Dmitry Baryshkov <dmitry.baryshkov@...aro.org>
To:     Bhupesh Sharma <bhupesh.sharma@...aro.org>
Cc:     linux-arm-msm@...r.kernel.org, linux-pci@...r.kernel.org,
        bhupesh.linux@...il.com, lorenzo.pieralisi@....com,
        agross@...nel.org, bjorn.andersson@...aro.org,
        svarbanov@...sol.com, bhelgaas@...gle.com,
        linux-kernel@...r.kernel.org, devicetree@...r.kernel.org,
        robh+dt@...nel.org, Vinod Koul <vkoul@...nel.org>
Subject: Re: [PATCH 4/6] PCI: qcom: Add SM8150 SoC support

On Wed, 23 Feb 2022 at 22:30, Bhupesh Sharma <bhupesh.sharma@...aro.org> wrote:
>
> The PCIe IP (rev 1.5.0) on SM8150 SoC is similar to the one used on
> SM8250. Hence the support is added reusing the members of ops_2_7_0.
>
> Cc: Vinod Koul <vkoul@...nel.org>
> Cc: Rob Herring <robh+dt@...nel.org>
> Signed-off-by: Bhupesh Sharma <bhupesh.sharma@...aro.org>

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@...aro.org>

> ---
>  drivers/pci/controller/dwc/pcie-qcom.c | 16 ++++++++++++++++
>  1 file changed, 16 insertions(+)
>
> diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c
> index c19cd506ed3f..66fbc0234888 100644
> --- a/drivers/pci/controller/dwc/pcie-qcom.c
> +++ b/drivers/pci/controller/dwc/pcie-qcom.c
> @@ -1487,6 +1487,17 @@ static const struct qcom_pcie_ops ops_1_9_0 = {
>         .config_sid = qcom_pcie_config_sid_sm8250,
>  };
>
> +/* Qcom IP rev.: 1.5.0 */
> +static const struct qcom_pcie_ops ops_1_5_0 = {
> +       .get_resources = qcom_pcie_get_resources_2_7_0,
> +       .init = qcom_pcie_init_2_7_0,
> +       .deinit = qcom_pcie_deinit_2_7_0,
> +       .ltssm_enable = qcom_pcie_2_3_2_ltssm_enable,
> +       .post_init = qcom_pcie_post_init_2_7_0,
> +       .post_deinit = qcom_pcie_post_deinit_2_7_0,
> +       .config_sid = qcom_pcie_config_sid_sm8250,
> +};
> +
>  static const struct qcom_pcie_cfg apq8084_cfg = {
>         .ops = &ops_1_0_0,
>  };
> @@ -1511,6 +1522,10 @@ static const struct qcom_pcie_cfg sdm845_cfg = {
>         .ops = &ops_2_7_0,
>  };
>
> +static const struct qcom_pcie_cfg sm8150_cfg = {
> +       .ops = &ops_1_5_0,
> +};
> +
>  static const struct qcom_pcie_cfg sm8250_cfg = {
>         .ops = &ops_1_9_0,
>  };
> @@ -1626,6 +1641,7 @@ static const struct of_device_id qcom_pcie_match[] = {
>         { .compatible = "qcom,pcie-ipq4019", .data = &ipq4019_cfg },
>         { .compatible = "qcom,pcie-qcs404", .data = &ipq4019_cfg },
>         { .compatible = "qcom,pcie-sdm845", .data = &sdm845_cfg },
> +       { .compatible = "qcom,pcie-sm8150", .data = &sm8150_cfg },
>         { .compatible = "qcom,pcie-sm8250", .data = &sm8250_cfg },
>         { .compatible = "qcom,pcie-sc8180x", .data = &sm8250_cfg },
>         { .compatible = "qcom,pcie-sc7280", .data = &sc7280_cfg },
> --
> 2.35.1
>


-- 
With best wishes
Dmitry