linux-kernel - Re: [PATCH v8 1/2] dt-bindings: timer: Add bindings for Intel Keem Bay SoC Timer

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <YhYa3tlTEcLct2xu@smile.fi.intel.com>
Date:   Wed, 23 Feb 2022 13:30:38 +0200
From:   Andy Shevchenko <andriy.shevchenko@...ux.intel.com>
To:     Rob Herring <robh@...nel.org>
Cc:     shruthi.sanil@...el.com, daniel.lezcano@...aro.org,
        tglx@...utronix.de, linux-kernel@...r.kernel.org,
        devicetree@...r.kernel.org, mgross@...ux.intel.com,
        srikanth.thokala@...el.com, lakshmi.bai.raja.subramanian@...el.com,
        mallikarjunappa.sangannavar@...el.com
Subject: Re: [PATCH v8 1/2] dt-bindings: timer: Add bindings for Intel Keem
 Bay SoC Timer

On Tue, Feb 22, 2022 at 05:13:41PM -0600, Rob Herring wrote:
> On Tue, Feb 22, 2022 at 03:26:53PM +0530, shruthi.sanil@...el.com wrote:
> > From: Shruthi Sanil <shruthi.sanil@...el.com>
> > 
> > Add Device Tree bindings for the Timer IP, which can be used as
> > clocksource and clockevent device in the Intel Keem Bay SoC.

...

> > +    soc {
> > +        #address-cells = <0x2>;
> > +        #size-cells = <0x2>;
> > +
> > +        gpt@...31000 {
> > +            compatible = "intel,keembay-gpt-creg", "simple-mfd";
> 
> It looks like you are splitting things based on Linux implementation
> details. Does this h/w block have different combinations of timers and
> counters? If not, then you don't need the child nodes at all. There's
> plenty of h/w blocks that get used as both a clocksource and clockevent.
> 
> Maybe I already raised this, but assume I don't remember and this patch
> needs to address any questions I already asked.

I dunno if I mentioned that hardware seems to have 5 or so devices behind
the block, so ideally it should be one device node that represents the global
register spaces and several children nodes.

However, I am not familiar with the established practices in DT world, but
above seems to me the right thing to do since it describes the hardware as
is (without any linuxisms).

> > +            reg = <0x0 0x20331000 0x0 0xc>;
> > +            ranges = <0x0 0x0 0x20330000 0xF0>;
> > +            #address-cells = <0x1>;
> > +            #size-cells = <0x1>;
> > +
> > +            counter@e8 {
> > +                compatible = "intel,keembay-counter";
> > +                reg = <0xe8 0x8>;
> > +                clocks = <&scmi_clk KEEM_BAY_A53_TIM>;
> > +            };
> > +
> > +            timer@30 {
> > +                compatible = "intel,keembay-timer";
> > +                reg = <0x30 0xc>;
> > +                interrupts = <GIC_SPI 0x5 IRQ_TYPE_LEVEL_HIGH>;
> > +                clocks = <&scmi_clk KEEM_BAY_A53_TIM>;
> > +            };
> > +        };
> > +    };

-- 
With Best Regards,
Andy Shevchenko