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Message-ID: <Yhev1BMkuqI5/Cu6@ripper>
Date: Thu, 24 Feb 2022 08:18:28 -0800
From: Bjorn Andersson <bjorn.andersson@...aro.org>
To: Ansuel Smith <ansuelsmth@...il.com>
Cc: Andy Gross <agross@...nel.org>,
Michael Turquette <mturquette@...libre.com>,
Stephen Boyd <sboyd@...nel.org>,
Rob Herring <robh+dt@...nel.org>,
Philipp Zabel <p.zabel@...gutronix.de>,
Taniya Das <tdas@...eaurora.org>,
linux-arm-msm@...r.kernel.org, linux-clk@...r.kernel.org,
devicetree@...r.kernel.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH v4 12/16] dt-bindings: clock: add ipq8064 ce5 clk define
On Thu 24 Feb 08:01 PST 2022, Ansuel Smith wrote:
> On Wed, Feb 23, 2022 at 10:01:14PM -0600, Bjorn Andersson wrote:
> > On Thu 17 Feb 17:56 CST 2022, Ansuel Smith wrote:
> >
> > > Add ipq8064 ce5 clk define needed for CryptoEngine in gcc driver.
> > >
> >
> > Reviewed-by: Bjorn Andersson <bjorn.andersson@...aro.org>
> >
> > > Signed-off-by: Ansuel Smith <ansuelsmth@...il.com>
> > > ---
> > > include/dt-bindings/clock/qcom,gcc-ipq806x.h | 5 ++++-
> > > 1 file changed, 4 insertions(+), 1 deletion(-)
> > >
> > > diff --git a/include/dt-bindings/clock/qcom,gcc-ipq806x.h b/include/dt-bindings/clock/qcom,gcc-ipq806x.h
> > > index 7deec14a6dee..02262d2ac899 100644
> > > --- a/include/dt-bindings/clock/qcom,gcc-ipq806x.h
> > > +++ b/include/dt-bindings/clock/qcom,gcc-ipq806x.h
> > > @@ -240,7 +240,7 @@
> > > #define PLL14 232
> > > #define PLL14_VOTE 233
> > > #define PLL18 234
> > > -#define CE5_SRC 235
> > > +#define CE5_A_CLK 235
> > > #define CE5_H_CLK 236
> > > #define CE5_CORE_CLK 237
> > > #define CE3_SLEEP_CLK 238
> > > @@ -283,5 +283,8 @@
> > > #define EBI2_AON_CLK 281
> > > #define NSSTCM_CLK_SRC 282
> > > #define NSSTCM_CLK 283
> >
> > You don't like 284?
> >
> > Regards,
> > Bjorn
> >
>
> In the QSDK 284 is used for a virtual clk used to scale the NSS core.
> I skipped that in case we will implement it and to keep these header
> similar across QSDK and linux.
>
Okay, let's take a look at how that virtual clock is implemented once
you get there. But I'm fine with the reasoning for leaving a gap.
Regards,
Bjorn
> > > +#define CE5_A_CLK_SRC 285
> > > +#define CE5_H_CLK_SRC 286
> > > +#define CE5_CORE_CLK_SRC 287
> > >
> > > #endif
> > > --
> > > 2.34.1
> > >
>
> --
> Ansuel
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