| lists.openwall.net | lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC | |
|
Open Source and information security mailing list archives
| ||
|
Message-ID: <20220224195326.e6atop2vitnl3w4l@ti.com>
Date: Fri, 25 Feb 2022 01:23:26 +0530
From: Pratyush Yadav <p.yadav@...com>
To: Tudor Ambarus <tudor.ambarus@...rochip.com>
CC: <michael@...le.cc>, <Takahiro.Kuwano@...ineon.com>,
<miquel.raynal@...tlin.com>, <richard@....at>, <vigneshr@...com>,
<linux-mtd@...ts.infradead.org>, <linux-kernel@...r.kernel.org>,
<nicolas.ferre@...rochip.com>, <zhengxunli@...c.com.tw>,
<jaimeliao@...c.com.tw>, <Bacem.Daassi@...ineon.com>
Subject: Re: [PATCH 3/3] mtd: spi-nor: spansion: Rework
spi_nor_cypress_octal_dtr_enable()
On 10/02/22 04:33AM, Tudor Ambarus wrote:
> Introduce template operation to remove code duplication.
> Split spi_nor_cypress_octal_dtr_enable() in
> spi_nor_cypress_octal_dtr_ena() spi_nor_cypress_octal_dtr_dis() as it no
> longer made sense to try to keep everything alltogether: too many
> "if (enable)" throughout the code, which made the code difficult to read.
>
> Signed-off-by: Tudor Ambarus <tudor.ambarus@...rochip.com>
> ---
> drivers/mtd/spi-nor/spansion.c | 135 ++++++++++++++++++---------------
> 1 file changed, 72 insertions(+), 63 deletions(-)
>
> diff --git a/drivers/mtd/spi-nor/spansion.c b/drivers/mtd/spi-nor/spansion.c
> index d69a569f31e4..9bb239f1e142 100644
> --- a/drivers/mtd/spi-nor/spansion.c
> +++ b/drivers/mtd/spi-nor/spansion.c
> @@ -19,85 +19,78 @@
> #define SPINOR_REG_CYPRESS_CFR5V_OCT_DTR_DS 0
> #define SPINOR_OP_CYPRESS_RD_FAST 0xee
>
> -/**
> - * spi_nor_cypress_octal_dtr_enable() - Enable octal DTR on Cypress flashes.
> - * @nor: pointer to a 'struct spi_nor'
> - * @enable: whether to enable or disable Octal DTR
> - *
> - * This also sets the memory access latency cycles to 24 to allow the flash to
> - * run at up to 200MHz.
> - *
> - * Return: 0 on success, -errno otherwise.
> - */
> -static int spi_nor_cypress_octal_dtr_enable(struct spi_nor *nor, bool enable)
> +/* Spansion/Cypress SPI NOR flash operations. */
> +#define SPI_NOR_SPANSION_WR_ANY_REG_OP(naddr, addr, ndata, buf) \
Same comments as before for variable and function names.
> + SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_WR_ANY_REG, 0), \
> + SPI_MEM_OP_ADDR(naddr, addr, 0), \
> + SPI_MEM_OP_NO_DUMMY, \
> + SPI_MEM_OP_DATA_OUT(ndata, buf, 0))
> +
> +static int spi_nor_cypress_octal_dtr_en(struct spi_nor *nor)
> {
> struct spi_mem_op op;
> u8 *buf = nor->bouncebuf;
> int ret;
>
> - if (enable) {
> - /* Use 24 dummy cycles for memory array reads. */
> - ret = spi_nor_write_enable(nor);
> - if (ret)
> - return ret;
> -
> - *buf = SPINOR_REG_CYPRESS_CFR2V_MEMLAT_11_24;
> - op = (struct spi_mem_op)
> - SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_WR_ANY_REG, 1),
> - SPI_MEM_OP_ADDR(3, SPINOR_REG_CYPRESS_CFR2V,
> - 1),
> - SPI_MEM_OP_NO_DUMMY,
> - SPI_MEM_OP_DATA_OUT(1, buf, 1));
> -
> - ret = spi_mem_exec_op(nor->spimem, &op);
> - if (ret)
> - return ret;
> -
> - ret = spi_nor_wait_till_ready(nor);
> - if (ret)
> - return ret;
> -
> - nor->read_dummy = 24;
> - }
> -
> - /* Set/unset the octal and DTR enable bits. */
> - ret = spi_nor_write_enable(nor);
> + /* Use 24 dummy cycles for memory array reads. */
> + *buf = SPINOR_REG_CYPRESS_CFR2V_MEMLAT_11_24;
> + op = (struct spi_mem_op)
> + SPI_NOR_SPANSION_WR_ANY_REG_OP(3, SPINOR_REG_CYPRESS_CFR2V,
> + 1, buf);
> +
> + ret = spi_nor_write_reg(nor, &op, nor->reg_proto);
> if (ret)
> return ret;
>
> - if (enable) {
> - buf[0] = SPINOR_REG_CYPRESS_CFR5V_OCT_DTR_EN;
> - } else {
> - /*
> - * The register is 1-byte wide, but 1-byte transactions are not
> - * allowed in 8D-8D-8D mode. Since there is no register at the
> - * next location, just initialize the value to 0 and let the
> - * transaction go on.
> - */
> - buf[0] = SPINOR_REG_CYPRESS_CFR5V_OCT_DTR_DS;
> - buf[1] = 0;
> - }
> + ret = spi_nor_wait_till_ready(nor);
> + if (ret)
> + return ret;
> +
> + nor->read_dummy = 24;
>
> + /* Set the octal and DTR enable bits. */
> + buf[0] = SPINOR_REG_CYPRESS_CFR5V_OCT_DTR_EN;
> op = (struct spi_mem_op)
> - SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_WR_ANY_REG, 1),
> - SPI_MEM_OP_ADDR(enable ? 3 : 4,
> - SPINOR_REG_CYPRESS_CFR5V,
> - 1),
> - SPI_MEM_OP_NO_DUMMY,
> - SPI_MEM_OP_DATA_OUT(enable ? 1 : 2, buf, 1));
> + SPI_NOR_SPANSION_WR_ANY_REG_OP(3, SPINOR_REG_CYPRESS_CFR5V,
> + 1, buf);
>
> - if (!enable)
> - spi_nor_spimem_setup_op(nor, &op, SNOR_PROTO_8_8_8_DTR);
> + ret = spi_nor_write_reg(nor, &op, nor->reg_proto);
> + if (ret)
> + return ret;
>
> - ret = spi_mem_exec_op(nor->spimem, &op);
> + /* Read flash ID to make sure the switch was successful. */
> + ret = spi_nor_read_id(nor, 4, 3, buf, SNOR_PROTO_8_8_8_DTR);
> + if (ret)
> + return ret;
> +
> + if (memcmp(buf, nor->info->id, nor->info->id_len))
> + return -EINVAL;
> +
> + return 0;
> +}
> +
> +static int spi_nor_cypress_octal_dtr_dis(struct spi_nor *nor)
> +{
> + struct spi_mem_op op;
> + u8 *buf = nor->bouncebuf;
> + int ret;
> +
> + /*
> + * The register is 1-byte wide, but 1-byte transactions are not allowed
> + * in 8D-8D-8D mode. Since there is no register at the next location,
> + * just initialize the value to 0 and let the transaction go on.
> + */
> + buf[0] = SPINOR_REG_CYPRESS_CFR5V_OCT_DTR_DS;
> + buf[1] = 0;
> + op = (struct spi_mem_op)
> + SPI_NOR_SPANSION_WR_ANY_REG_OP(4, SPINOR_REG_CYPRESS_CFR5V,
> + 2, buf);
> + ret = spi_nor_write_reg(nor, &op, SNOR_PROTO_8_8_8_DTR);
> if (ret)
> return ret;
>
> /* Read flash ID to make sure the switch was successful. */
> - if (enable)
> - ret = spi_nor_read_id(nor, 4, 3, buf, SNOR_PROTO_8_8_8_DTR);
> - else
> - ret = spi_nor_read_id(nor, 0, 0, buf, nor->reg_proto);
> + ret = spi_nor_read_id(nor, 0, 0, buf, nor->reg_proto);
As with previous patch, this won't work.
I have not tested on this flash yet. I will wait for a re-roll.
> if (ret)
> return ret;
>
> @@ -107,6 +100,22 @@ static int spi_nor_cypress_octal_dtr_enable(struct spi_nor *nor, bool enable)
> return 0;
> }
>
> +/**
> + * spi_nor_cypress_octal_dtr_enable() - Enable octal DTR on Cypress flashes.
> + * @nor: pointer to a 'struct spi_nor'
> + * @enable: whether to enable or disable Octal DTR
> + *
> + * This also sets the memory access latency cycles to 24 to allow the flash to
> + * run at up to 200MHz.
> + *
> + * Return: 0 on success, -errno otherwise.
> + */
> +static int spi_nor_cypress_octal_dtr_enable(struct spi_nor *nor, bool enable)
> +{
> + return enable ? spi_nor_cypress_octal_dtr_en(nor) :
> + spi_nor_cypress_octal_dtr_dis(nor);
> +}
> +
> static void s28hs512t_default_init(struct spi_nor *nor)
> {
> nor->params->octal_dtr_enable = spi_nor_cypress_octal_dtr_enable;
> --
> 2.25.1
>
--
Regards,
Pratyush Yadav
Texas Instruments Inc.
Powered by blists - more mailing lists