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Message-ID: <20220224201344.GA291052@bhelgaas>
Date: Thu, 24 Feb 2022 14:13:44 -0600
From: Bjorn Helgaas <helgaas@...nel.org>
To: Pali Rohár <pali@...nel.org>
Cc: Lorenzo Pieralisi <lorenzo.pieralisi@....com>,
Bjorn Helgaas <bhelgaas@...gle.com>,
Rob Herring <robh+dt@...nel.org>, Andrew Lunn <andrew@...n.ch>,
Thomas Petazzoni <thomas.petazzoni@...tlin.com>,
Krzysztof Wilczyński <kw@...ux.com>,
Marek Behún <kabel@...nel.org>,
Russell King <rmk+kernel@...linux.org.uk>,
Gregory Clement <gregory.clement@...tlin.com>,
linux-pci@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
linux-kernel@...r.kernel.org
Subject: Re: [PATCH 1/6] PCI: Add PCI_EXP_SLTCTL_ASPL_DISABLE macro
On Tue, Feb 22, 2022 at 05:31:53PM +0100, Pali Rohár wrote:
> Add macro defining Auto Slot Power Limit Disable bit in Slot Control
> Register.
>
> Signed-off-by: Pali Rohár <pali@...nel.org>
> Signed-off-by: Marek Behún <kabel@...nel.org>
Acked-by: Bjorn Helgaas <bhelgaas@...gle.com>
> ---
> include/uapi/linux/pci_regs.h | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h
> index bee1a9ed6e66..108f8523fa04 100644
> --- a/include/uapi/linux/pci_regs.h
> +++ b/include/uapi/linux/pci_regs.h
> @@ -616,6 +616,7 @@
> #define PCI_EXP_SLTCTL_PWR_OFF 0x0400 /* Power Off */
> #define PCI_EXP_SLTCTL_EIC 0x0800 /* Electromechanical Interlock Control */
> #define PCI_EXP_SLTCTL_DLLSCE 0x1000 /* Data Link Layer State Changed Enable */
> +#define PCI_EXP_SLTCTL_ASPL_DISABLE 0x2000 /* Auto Slot Power Limit Disable */
> #define PCI_EXP_SLTCTL_IBPD_DISABLE 0x4000 /* In-band PD disable */
> #define PCI_EXP_SLTSTA 0x1a /* Slot Status */
> #define PCI_EXP_SLTSTA_ABP 0x0001 /* Attention Button Pressed */
> --
> 2.20.1
>
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