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Message-Id: <20220224235653.BC79DC340E9@smtp.kernel.org>
Date: Thu, 24 Feb 2022 15:56:51 -0800
From: Stephen Boyd <sboyd@...nel.org>
To: Rohit Agarwal <quic_rohiagar@...cinc.com>, agross@...nel.org,
bjorn.andersson@...aro.org, manivannan.sadhasivam@...aro.org,
mturquette@...libre.com, robh+dt@...nel.org
Cc: linux-arm-msm@...r.kernel.org, linux-clk@...r.kernel.org,
devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
Rohit Agarwal <quic_rohiagar@...cinc.com>
Subject: Re: [PATCH v4 3/5] ARM: dts: qcom: sdx65: Add support for A7 PLL clock
Quoting Rohit Agarwal (2022-02-21 20:56:23)
> On SDX65 there is a separate A7 PLL which is used to provide high
> frequency clock to the Cortex A7 CPU via a MUX.
>
> Signed-off-by: Rohit Agarwal <quic_rohiagar@...cinc.com>
> ---
Reviewed-by: Stephen Boyd <sboyd@...nel.org>
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