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Message-ID: <Yhj+DrSDF6VQWe6X@robh.at.kernel.org>
Date: Fri, 25 Feb 2022 10:04:30 -0600
From: Rob Herring <robh@...nel.org>
To: "Peng Fan (OSS)" <peng.fan@....nxp.com>
Cc: aisheng.dong@....com, festevam@...il.com, shawnguo@...nel.org,
stefan@...er.ch, kernel@...gutronix.de, linus.walleij@...aro.org,
linux-imx@....com, linux-gpio@...r.kernel.org,
devicetree@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
linux-kernel@...r.kernel.org, Peng Fan <peng.fan@....com>
Subject: Re: [PATCH 1/2] dt-bindings: pinctrl: imx93: Add pinctrl binding
On Tue, Feb 15, 2022 at 04:20:05PM +0800, Peng Fan (OSS) wrote:
> From: Peng Fan <peng.fan@....com>
>
> Add pinctrl binding doc for i.MX93
>
> Signed-off-by: Peng Fan <peng.fan@....com>
> ---
> .../bindings/pinctrl/fsl,imx93-pinctrl.yaml | 85 +++++++++++++++++++
> 1 file changed, 85 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/pinctrl/fsl,imx93-pinctrl.yaml
>
> diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,imx93-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/fsl,imx93-pinctrl.yaml
> new file mode 100644
> index 000000000000..95c87ea4c5c8
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/pinctrl/fsl,imx93-pinctrl.yaml
> @@ -0,0 +1,85 @@
> +# SPDX-License-Identifier: GPL-2.0
Dual license. checkpatch will tell you this and which ones.
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/pinctrl/fsl,imx93-pinctrl.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Freescale IMX93 IOMUX Controller
> +
> +maintainers:
> + - Peng Fan <peng.fan@....com>
> +
> +description:
> + Please refer to fsl,imx-pinctrl.txt and pinctrl-bindings.txt in this directory
> + for common binding part and usage.
> +
> +properties:
> + compatible:
> + const: fsl,imx93-iomuxc
> +
> + reg:
> + maxItems: 1
> +
> +# Client device subnode's properties
> +patternProperties:
> + 'grp$':
> + type: object
> + description:
> + Pinctrl node's client devices use subnodes for desired pin configuration.
> + Client device subnodes use below standard properties.
> +
> + properties:
> + fsl,pins:
> + description:
> + each entry consists of 6 integers and represents the mux and config
> + setting for one pin. The first 5 integers <mux_reg conf_reg input_reg
> + mux_val input_val> are specified using a PIN_FUNC_ID macro, which can
> + be found in <arch/arm64/boot/dts/freescale/imx8mp-pinfunc.h>. The last
> + integer CONFIG is the pad setting value like pull-up on this pin. Please
> + refer to i.MX8M Plus Reference Manual for detailed CONFIG settings.
> + $ref: /schemas/types.yaml#/definitions/uint32-matrix
> + items:
> + items:
> + - description: |
> + "mux_reg" indicates the offset of mux register.
> + - description: |
> + "conf_reg" indicates the offset of pad configuration register.
> + - description: |
> + "input_reg" indicates the offset of select input register.
> + - description: |
> + "mux_val" indicates the mux value to be applied.
> + - description: |
> + "input_val" indicates the select input value to be applied.
> + - description: |
> + "pad_setting" indicates the pad configuration value to be applied.
> +
> +
> + required:
> + - fsl,pins
> +
> + additionalProperties: false
> +
> +allOf:
> + - $ref: "pinctrl.yaml#"
Move this above 'properties'
> +
> +required:
> + - compatible
> + - reg
> +
> +additionalProperties: false
> +
> +examples:
> + # Pinmux controller node
> + - |
> + iomuxc: pinctrl@...c0000 {
> + compatible = "fsl,imx93-iomuxc";
> + reg = <0x30330000 0x10000>;
> +
> + pinctrl_uart3: uart3grp {
> + fsl,pins =
> + <0x48 0x1f8 0x41c 0x1 0x0 0x49>,
> + <0x4c 0x1fc 0x418 0x1 0x0 0x49>;
> + };
> + };
> +
> +...
> --
> 2.25.1
>
>
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