linux-kernel - Re: [PATCH 5/6] PCI: mvebu: Add support for sending Set_Slot_Power

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <20220225170225.GA363593@bhelgaas>
Date:   Fri, 25 Feb 2022 11:02:25 -0600
From:   Bjorn Helgaas <helgaas@...nel.org>
To:     Pali Rohár <pali@...nel.org>
Cc:     Lorenzo Pieralisi <lorenzo.pieralisi@....com>,
        Bjorn Helgaas <bhelgaas@...gle.com>,
        Rob Herring <robh+dt@...nel.org>, Andrew Lunn <andrew@...n.ch>,
        Thomas Petazzoni <thomas.petazzoni@...tlin.com>,
        Krzysztof Wilczyński <kw@...ux.com>,
        Marek Behún <kabel@...nel.org>,
        Russell King <rmk+kernel@...linux.org.uk>,
        Gregory Clement <gregory.clement@...tlin.com>,
        linux-pci@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
        linux-kernel@...r.kernel.org
Subject: Re: [PATCH 5/6] PCI: mvebu: Add support for sending
 Set_Slot_Power_Limit message

On Fri, Feb 25, 2022 at 01:54:07PM +0100, Pali Rohár wrote:
> On Thursday 24 February 2022 15:28:11 Bjorn Helgaas wrote:
> > On Tue, Feb 22, 2022 at 05:31:57PM +0100, Pali Rohár wrote:
> > > This PCIe message is sent automatically by mvebu HW when link changes
> > > status from down to up.

> > PCIe r6.0, sec 2.2.8.5 and 7.5.3.9, also say Set_Slot_Power_Limit must
> > be sent on a config write to Slot Capabilities.  I don't really
> > understand that, since AFAICS, everything in that register is
> > read-only.  But there must be some use case for forcing a message.
> 
> I understood it in this way: Capabilities register is read-only hw-init
> and so firmware / driver can write initialization values into this
> register. And when firmware / driver is doing this write then Root port
> should send that Set_Slot_Power_Limit message.

Sec 7.5.3.9 describes the behavior of Slot Capabilities in config
space, where it must be read-only.  Firmware (or the mvebu driver)
must use a different mechanism to initialize the values.

FWIW, I found this implementation note in PCIe r6.0, sec 6.9 that
explains why config writes to this read-only register would be useful:

  IMPLEMENTATION NOTE: AUTO SLOT POWER LIMIT DISABLE

  In some environments host software may wish to directly manage the
  transmission of a Set_Slot_Power_Limit message by performing a
  Configuration Write to the Slot Capabilities register rather than
  have the transmission automatically occur when the Link transitions
  from a non-DL_Up to a DL_Up status. This allows host software to
  limit power supply surge current by staggering the transition of
  Endpoints to a higher power state following a Link Down or when
  multiple Endpoints are simultaneously hot-added due to cable or
  adapter insertion.

Bjorn