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Message-ID: <4fbeeae8-0b56-e665-744f-6a1ca2b24f9e@marcan.st>
Date: Sat, 26 Feb 2022 07:05:26 +0900
From: Hector Martin <marcan@...can.st>
To: Marc Zyngier <maz@...nel.org>
Cc: Thomas Gleixner <tglx@...utronix.de>,
Rob Herring <robh+dt@...nel.org>,
Sven Peter <sven@...npeter.dev>,
Alyssa Rosenzweig <alyssa@...enzweig.io>,
Mark Kettenis <mark.kettenis@...all.nl>,
linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org,
devicetree@...r.kernel.org
Subject: Re: [PATCH v2 7/7] irqchip/apple-aic: Add support for AICv2
On 26/02/2022 00.27, Marc Zyngier wrote:
> On Thu, 24 Feb 2022 13:07:41 +0000,
> Hector Martin <marcan@...can.st> wrote:
>> - /*
>> - * Make sure the kernel's idea of logical CPU order is the same as AIC's
>> - * If we ever end up with a mismatch here, we will have to introduce
>> - * a mapping table similar to what other irqchip drivers do.
>> - */
>> - WARN_ON(aic_ic_read(aic_irqc, AIC_WHOAMI) != smp_processor_id());
>> + if (aic_irqc->info.version == 1) {
>> + /*
>> + * Make sure the kernel's idea of logical CPU order is the same as AIC's
>> + * If we ever end up with a mismatch here, we will have to introduce
>> + * a mapping table similar to what other irqchip drivers do.
>> + */
>> + WARN_ON(aic_ic_read(aic_irqc, AIC_WHOAMI) != smp_processor_id());
>
> Don't you have a similar issue with AICv2? Or is it that AICv2
> doesn't have this register?
No concept of individual CPUs in AICv2 at all, so no WHOAMI register
either :)
--
Hector Martin (marcan@...can.st)
Public Key: https://mrcn.st/pub
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