linux-kernel - [PATCH 2/2] clk: imx8mq: add 27m phy pll ref clock

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Message-Id: <20220225090002.2497057-3-peng.fan@oss.nxp.com>
Date:   Fri, 25 Feb 2022 17:00:02 +0800
From:   "Peng Fan (OSS)" <peng.fan@....nxp.com>
To:     sboyd@...nel.org, robh+dt@...nel.org, shawnguo@...nel.org,
        s.hauer@...gutronix.de, abel.vesa@....com
Cc:     kernel@...gutronix.de, festevam@...il.com, linux-imx@....com,
        linux-clk@...r.kernel.org, devicetree@...r.kernel.org,
        linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org,
        Peng Fan <peng.fan@....com>
Subject: [PATCH 2/2] clk: imx8mq: add 27m phy pll ref clock

From: Peng Fan <peng.fan@....com>

According to pll documentation, the 3rd pll ref clock should be
hdmi phy 27m clock, not dummy clock.

Signed-off-by: Peng Fan <peng.fan@....com>
---
 drivers/clk/imx/clk-imx8mq.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/clk/imx/clk-imx8mq.c b/drivers/clk/imx/clk-imx8mq.c
index 83cc2b1c3294..a9e69b6355ed 100644
--- a/drivers/clk/imx/clk-imx8mq.c
+++ b/drivers/clk/imx/clk-imx8mq.c
@@ -25,7 +25,7 @@ static u32 share_count_sai6;
 static u32 share_count_dcss;
 static u32 share_count_nand;
 
-static const char * const pll_ref_sels[] = { "osc_25m", "osc_27m", "dummy", "dummy", };
+static const char * const pll_ref_sels[] = { "osc_25m", "osc_27m", "hdmi_phy_27m", "dummy", };
 static const char * const arm_pll_bypass_sels[] = {"arm_pll", "arm_pll_ref_sel", };
 static const char * const gpu_pll_bypass_sels[] = {"gpu_pll", "gpu_pll_ref_sel", };
 static const char * const vpu_pll_bypass_sels[] = {"vpu_pll", "vpu_pll_ref_sel", };
-- 
2.25.1