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Message-ID: <20220225133137.813919-11-gabriel.fernandez@foss.st.com>
Date: Fri, 25 Feb 2022 14:31:34 +0100
From: <gabriel.fernandez@...s.st.com>
To: Michael Turquette <mturquette@...libre.com>,
Stephen Boyd <sboyd@...nel.org>,
Rob Herring <robh+dt@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski@...onical.com>,
Maxime Coquelin <mcoquelin.stm32@...il.com>,
Alexandre Torgue <alexandre.torgue@...s.st.com>,
Philipp Zabel <p.zabel@...gutronix.de>,
Gabriel Fernandez <gabriel.fernandez@...s.st.com>
CC: <linux-clk@...r.kernel.org>, <devicetree@...r.kernel.org>,
<linux-stm32@...md-mailman.stormreply.com>,
<linux-arm-kernel@...ts.infradead.org>,
<linux-kernel@...r.kernel.org>
Subject: [PATCH v2 10/13] clk: stm32mp13: add multi mux function
From: Gabriel Fernandez <gabriel.fernandez@...s.st.com>
Some RCC muxes can manages two output clocks with same register.
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@...s.st.com>
---
drivers/clk/stm32/clk-stm32-core.c | 10 ++++++++++
drivers/clk/stm32/clk-stm32-core.h | 2 ++
drivers/clk/stm32/clk-stm32mp13.c | 30 ++++++++++++++++++++++++++++++
3 files changed, 42 insertions(+)
diff --git a/drivers/clk/stm32/clk-stm32-core.c b/drivers/clk/stm32/clk-stm32-core.c
index fc32e62e0b44..69cfa2d1b8e2 100644
--- a/drivers/clk/stm32/clk-stm32-core.c
+++ b/drivers/clk/stm32/clk-stm32-core.c
@@ -480,6 +480,16 @@ int clk_stm32_composite_set_parent(struct clk_hw *hw, u8 index)
spin_unlock_irqrestore(composite->lock, flags);
+ if (composite->clock_data->is_multi_mux) {
+ struct clk_hw *other_mux_hw = composite->clock_data->is_multi_mux(hw);
+
+ if (other_mux_hw) {
+ struct clk_hw *hwp = clk_hw_get_parent_by_index(hw, index);
+
+ clk_hw_reparent(other_mux_hw, hwp);
+ }
+ }
+
return 0;
}
diff --git a/drivers/clk/stm32/clk-stm32-core.h b/drivers/clk/stm32/clk-stm32-core.h
index 8ffa700323b8..61a7b4bb6a19 100644
--- a/drivers/clk/stm32/clk-stm32-core.h
+++ b/drivers/clk/stm32/clk-stm32-core.h
@@ -61,6 +61,7 @@ struct clk_stm32_clock_data {
const struct stm32_gate_cfg *gates;
const struct stm32_mux_cfg *muxes;
const struct stm32_div_cfg *dividers;
+ struct clk_hw *(*is_multi_mux)(struct clk_hw *hw);
};
struct stm32_rcc_match_data {
@@ -72,6 +73,7 @@ struct stm32_rcc_match_data {
u32 clear_offset;
int (*check_security)(void __iomem *base,
const struct clock_config *cfg);
+ int (*multi_mux)(void __iomem *base, const struct clock_config *cfg);
};
int stm32_rcc_reset_init(struct device *dev, const struct of_device_id *match,
diff --git a/drivers/clk/stm32/clk-stm32mp13.c b/drivers/clk/stm32/clk-stm32mp13.c
index 462e00877474..783a54e08439 100644
--- a/drivers/clk/stm32/clk-stm32mp13.c
+++ b/drivers/clk/stm32/clk-stm32mp13.c
@@ -1429,6 +1429,35 @@ static int stm32mp13_clock_is_provided_by_secure(void __iomem *base,
return 0;
}
+struct multi_mux {
+ struct clk_hw *hw1;
+ struct clk_hw *hw2;
+};
+
+static struct multi_mux *stm32_mp13_multi_mux[MUX_NB] = {
+ [MUX_SPI23] = &(struct multi_mux){ &spi2_k.hw, &spi3_k.hw },
+ [MUX_I2C12] = &(struct multi_mux){ &i2c1_k.hw, &i2c2_k.hw },
+ [MUX_LPTIM45] = &(struct multi_mux){ &lptim4_k.hw, &lptim5_k.hw },
+ [MUX_UART35] = &(struct multi_mux){ &usart3_k.hw, &uart5_k.hw },
+ [MUX_UART78] = &(struct multi_mux){ &uart7_k.hw, &uart8_k.hw },
+ [MUX_SAI1] = &(struct multi_mux){ &sai1_k.hw, &adfsdm_k.hw },
+};
+
+static struct clk_hw *stm32mp13_is_multi_mux(struct clk_hw *hw)
+{
+ struct clk_stm32_composite *composite = to_clk_stm32_composite(hw);
+ struct multi_mux *mmux = stm32_mp13_multi_mux[composite->mux_id];
+
+ if (mmux) {
+ if (!(mmux->hw1 == hw))
+ return mmux->hw1;
+ else
+ return mmux->hw2;
+ }
+
+ return NULL;
+}
+
u16 stm32mp13_cpt_gate[GATE_NB];
struct clk_stm32_clock_data stm32mp13_clock_data = {
@@ -1436,6 +1465,7 @@ struct clk_stm32_clock_data stm32mp13_clock_data = {
.gates = stm32mp13_gates,
.muxes = stm32mp13_muxes,
.dividers = stm32mp13_dividers,
+ .is_multi_mux = stm32mp13_is_multi_mux,
};
static const struct stm32_rcc_match_data stm32mp13_data = {
--
2.25.1
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