[<prev] [next>] [thread-next>] [day] [month] [year] [list]
Message-Id: <20220226135724.61516-1-linux@fw-web.de>
Date: Sat, 26 Feb 2022 14:57:24 +0100
From: Frank Wunderlich <linux@...web.de>
To: linux-rockchip@...ts.infradead.org
Cc: Frank Wunderlich <frank-w@...lic-files.de>,
Rob Herring <robh+dt@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski@...onical.com>,
Heiko Stuebner <heiko@...ech.de>,
Peter Geis <pgwipeout@...il.com>,
Michael Riesch <michael.riesch@...fvision.net>,
devicetree@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
linux-kernel@...r.kernel.org
Subject: [PATCH v1] arm64: dts: rockchip: Add sata2 node to rk356x
From: Frank Wunderlich <frank-w@...lic-files.de>
RK356x supports up to 3 sata controllers which were compatible with the
existing snps,dwc-ahci binding.
My board has only sata2 connected to combphy2 so only add this one.
Signed-off-by: Frank Wunderlich <frank-w@...lic-files.de>
---
arch/arm64/boot/dts/rockchip/rk356x.dtsi | 15 +++++++++++++++
1 file changed, 15 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk356x.dtsi b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
index 7cdef800cb3c..7b6c8a0c8b84 100644
--- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
@@ -230,6 +230,21 @@ scmi_shmem: sram@0 {
};
};
+ sata2: sata@...00000 {
+ compatible = "snps,dwc-ahci";
+ reg = <0 0xfc800000 0 0x1000>;
+ clocks = <&cru ACLK_SATA2>, <&cru CLK_SATA2_PMALIVE>,
+ <&cru CLK_SATA2_RXOOB>;
+ clock-names = "sata", "pmalive", "rxoob";
+ interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "hostc";
+ phys = <&combphy2 PHY_TYPE_SATA>;
+ phy-names = "sata-phy";
+ ports-implemented = <0x1>;
+ power-domains = <&power RK3568_PD_PIPE>;
+ status = "disabled";
+ };
+
gic: interrupt-controller@...00000 {
compatible = "arm,gic-v3";
reg = <0x0 0xfd400000 0 0x10000>, /* GICD */
--
2.25.1
Powered by blists - more mailing lists