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Message-Id: <20220227132640.3-1-sidongli1997@gmail.com>
Date: Sun, 27 Feb 2022 21:26:40 +0800
From: Dongli Si <kvmx86@...il.com>
To: peterz@...radead.org, joerg.roedel@....com
Cc: liam.merwick@...cle.com, kim.phillips@....com, mingo@...hat.com,
acme@...nel.org, mark.rutland@....com,
alexander.shishkin@...ux.intel.com, jolsa@...nel.org,
namhyung@...nel.org, tglx@...utronix.de, bp@...en8.de,
dave.hansen@...ux.intel.com, x86@...nel.org, hpa@...or.com,
linux-perf-users@...r.kernel.org, linux-kernel@...r.kernel.org
Subject: [PATCH] perf/x86/amd: Don't touch the Host-only bit inside the guest hypervisor
From: Dongli Si <sidongli1997@...il.com>
When using nested virtualization and if use "perf record" in an AMD Rome
and Milan guest hypervisor (L1), dmesg report an error message like this:
[ ] unchecked MSR access error: WRMSR to 0xc0010200 (tried to write 0x0000020000510076) at rIP: 0xffffffff81003a50 (x86_pmu_enable_all+0x60/0x100)
The AMD64_EVENTSEL_HOSTONLY bit is defined and used on the host, while
the guest hypervisor (L1) performance monitor unit should avoid such use.
Fixes: 1018faa6cf23 ("perf/x86/kvm: Fix Host-Only/Guest-Only counting with SVM disabled")
Signed-off-by: Dongli Si <sidongli1997@...il.com>
---
arch/x86/events/amd/core.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/arch/x86/events/amd/core.c b/arch/x86/events/amd/core.c
index 9687a8aef01c..3fafd1e46ada 100644
--- a/arch/x86/events/amd/core.c
+++ b/arch/x86/events/amd/core.c
@@ -8,6 +8,7 @@
#include <linux/jiffies.h>
#include <asm/apicdef.h>
#include <asm/nmi.h>
+#include <asm/hypervisor.h>
#include "../perf_event.h"
@@ -1027,7 +1028,8 @@ void amd_pmu_enable_virt(void)
{
struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
- cpuc->perf_ctr_virt_mask = 0;
+ if (hypervisor_is_type(X86_HYPER_NATIVE))
+ cpuc->perf_ctr_virt_mask = 0;
/* Reload all events */
amd_pmu_disable_all();
--
2.32.0
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