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Message-Id: <20220227203744.18355-2-prabhakar.mahadev-lad.rj@bp.renesas.com>
Date: Sun, 27 Feb 2022 20:37:33 +0000
From: Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
To: Geert Uytterhoeven <geert+renesas@...der.be>,
Magnus Damm <magnus.damm@...il.com>,
Rob Herring <robh+dt@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski@...onical.com>,
linux-renesas-soc@...r.kernel.org, devicetree@...r.kernel.org
Cc: Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>,
linux-kernel@...r.kernel.org,
Prabhakar <prabhakar.csengg@...il.com>,
Biju Das <biju.das.jz@...renesas.com>
Subject: [PATCH 01/12] arm64: dts: renesas: r9a07g054: Fillup the SDHI{0,1} stub nodes
Fillup the SDHI{0,1} stub nodes in RZ/V2L (R9A07G054) SoC DTSI.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
Reviewed-by: Biju Das <biju.das.jz@...renesas.com>
---
arch/arm64/boot/dts/renesas/r9a07g054.dtsi | 26 ++++++++++++++++++++--
1 file changed, 24 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi
index 3ddf0f24071c..0b0e924e28ae 100644
--- a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi
@@ -398,13 +398,35 @@
};
sdhi0: mmc@...00000 {
+ compatible = "renesas,sdhi-r9a07g054",
+ "renesas,rcar-gen3-sdhi";
reg = <0x0 0x11c00000 0 0x10000>;
- /* place holder */
+ interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD R9A07G054_SDHI0_IMCLK>,
+ <&cpg CPG_MOD R9A07G054_SDHI0_CLK_HS>,
+ <&cpg CPG_MOD R9A07G054_SDHI0_IMCLK2>,
+ <&cpg CPG_MOD R9A07G054_SDHI0_ACLK>;
+ clock-names = "core", "clkh", "cd", "aclk";
+ resets = <&cpg R9A07G054_SDHI0_IXRST>;
+ power-domains = <&cpg>;
+ status = "disabled";
};
sdhi1: mmc@...10000 {
+ compatible = "renesas,sdhi-r9a07g054",
+ "renesas,rcar-gen3-sdhi";
reg = <0x0 0x11c10000 0 0x10000>;
- /* place holder */
+ interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD R9A07G054_SDHI1_IMCLK>,
+ <&cpg CPG_MOD R9A07G054_SDHI1_CLK_HS>,
+ <&cpg CPG_MOD R9A07G054_SDHI1_IMCLK2>,
+ <&cpg CPG_MOD R9A07G054_SDHI1_ACLK>;
+ clock-names = "core", "clkh", "cd", "aclk";
+ resets = <&cpg R9A07G054_SDHI1_IXRST>;
+ power-domains = <&cpg>;
+ status = "disabled";
};
eth0: ethernet@...20000 {
--
2.17.1
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