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Message-Id: <20220227203744.18355-8-prabhakar.mahadev-lad.rj@bp.renesas.com>
Date: Sun, 27 Feb 2022 20:37:39 +0000
From: Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
To: Geert Uytterhoeven <geert+renesas@...der.be>,
Magnus Damm <magnus.damm@...il.com>,
Rob Herring <robh+dt@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski@...onical.com>,
linux-renesas-soc@...r.kernel.org, devicetree@...r.kernel.org
Cc: Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>,
linux-kernel@...r.kernel.org,
Prabhakar <prabhakar.csengg@...il.com>,
Biju Das <biju.das.jz@...renesas.com>
Subject: [PATCH 07/12] arm64: dts: renesas: r9a07g054: Fillup the OSTM{0,1,2} stub nodes
Fillup the OSTM{0,1,2} stub nodes in RZ/V2L (R9A07G054) SoC DTSI.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
Reviewed-by: Biju Das <biju.das.jz@...renesas.com>
---
arch/arm64/boot/dts/renesas/r9a07g054.dtsi | 24 +++++++++++++++++++---
1 file changed, 21 insertions(+), 3 deletions(-)
diff --git a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi
index 1207a99bf3fe..50cb2f0e6e73 100644
--- a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi
@@ -629,18 +629,36 @@
};
ostm0: timer@...01000 {
+ compatible = "renesas,r9a07g054-ostm",
+ "renesas,ostm";
reg = <0x0 0x12801000 0x0 0x400>;
- /* place holder */
+ interrupts = <GIC_SPI 46 IRQ_TYPE_EDGE_RISING>;
+ clocks = <&cpg CPG_MOD R9A07G054_OSTM0_PCLK>;
+ resets = <&cpg R9A07G054_OSTM0_PRESETZ>;
+ power-domains = <&cpg>;
+ status = "disabled";
};
ostm1: timer@...01400 {
+ compatible = "renesas,r9a07g054-ostm",
+ "renesas,ostm";
reg = <0x0 0x12801400 0x0 0x400>;
- /* place holder */
+ interrupts = <GIC_SPI 47 IRQ_TYPE_EDGE_RISING>;
+ clocks = <&cpg CPG_MOD R9A07G054_OSTM1_PCLK>;
+ resets = <&cpg R9A07G054_OSTM1_PRESETZ>;
+ power-domains = <&cpg>;
+ status = "disabled";
};
ostm2: timer@...01800 {
+ compatible = "renesas,r9a07g054-ostm",
+ "renesas,ostm";
reg = <0x0 0x12801800 0x0 0x400>;
- /* place holder */
+ interrupts = <GIC_SPI 48 IRQ_TYPE_EDGE_RISING>;
+ clocks = <&cpg CPG_MOD R9A07G054_OSTM2_PCLK>;
+ resets = <&cpg R9A07G054_OSTM2_PRESETZ>;
+ power-domains = <&cpg>;
+ status = "disabled";
};
};
--
2.17.1
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