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Date: Mon, 28 Feb 2022 11:13:30 +0300
From: Dmitry Baryshkov <dmitry.baryshkov@...aro.org>
To: Bjorn Andersson <bjorn.andersson@...aro.org>
Cc: Mathieu Poirier <mathieu.poirier@...aro.org>,
Rob Herring <robh+dt@...nel.org>,
linux-arm-msm@...r.kernel.org, linux-remoteproc@...r.kernel.org,
devicetree@...r.kernel.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH 12/13] arm64: dts: qcom: sm8450: Add remoteproc enablers
and instances
On Fri, 28 Jan 2022 at 05:55, Bjorn Andersson
<bjorn.andersson@...aro.org> wrote:
>
> The Qualcomm SM8450 carries the familiar set of audio, compute, sensor
> and modem remoteprocs. Add these and their dependencies.
>
> Signed-off-by: Bjorn Andersson <bjorn.andersson@...aro.org>
> ---
> arch/arm64/boot/dts/qcom/sm8450.dtsi | 297 +++++++++++++++++++++++++++
> 1 file changed, 297 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi
> index 10c25ad2d0c7..24fb3d3e667b 100644
> --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi
> @@ -7,6 +7,7 @@
> #include <dt-bindings/clock/qcom,gcc-sm8450.h>
> #include <dt-bindings/clock/qcom,rpmh.h>
> #include <dt-bindings/gpio/gpio.h>
> +#include <dt-bindings/mailbox/qcom-ipcc.h>
> #include <dt-bindings/power/qcom-rpmpd.h>
> #include <dt-bindings/soc/qcom,rpmh-rsc.h>
>
> @@ -460,6 +461,15 @@ cvp_mem: memory@...00000 {
> no-map;
> };
>
> + rmtfs_mem: memory@...00000 {
> + compatible = "qcom,rmtfs-mem";
> + reg = <0x0 0x9fd00000 0x0 0x280000>;
> + no-map;
> +
> + qcom,client-id = <1>;
> + qcom,vmid = <15>;
> + };
> +
> global_sync_mem: memory@...00000 {
> reg = <0x0 0xa6f00000 0x0 0x100000>;
> no-map;
> @@ -540,6 +550,113 @@ trusted_apps_ext_mem: memory@...00000 {
> };
> };
>
> + smp2p-adsp {
> + compatible = "qcom,smp2p";
> + qcom,smem = <443>, <429>;
> + interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
> + IPCC_MPROC_SIGNAL_SMP2P
> + IRQ_TYPE_EDGE_RISING>;
> + mboxes = <&ipcc IPCC_CLIENT_LPASS
> + IPCC_MPROC_SIGNAL_SMP2P>;
> +
> + qcom,local-pid = <0>;
> + qcom,remote-pid = <2>;
> +
> + smp2p_adsp_out: master-kernel {
> + qcom,entry-name = "master-kernel";
> + #qcom,smem-state-cells = <1>;
> + };
> +
> + smp2p_adsp_in: slave-kernel {
> + qcom,entry-name = "slave-kernel";
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> + };
> +
> + smp2p-cdsp {
> + compatible = "qcom,smp2p";
> + qcom,smem = <94>, <432>;
> + interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
> + IPCC_MPROC_SIGNAL_SMP2P
> + IRQ_TYPE_EDGE_RISING>;
> + mboxes = <&ipcc IPCC_CLIENT_CDSP
> + IPCC_MPROC_SIGNAL_SMP2P>;
> +
> + qcom,local-pid = <0>;
> + qcom,remote-pid = <5>;
> +
> + smp2p_cdsp_out: master-kernel {
> + qcom,entry-name = "master-kernel";
> + #qcom,smem-state-cells = <1>;
> + };
> +
> + smp2p_cdsp_in: slave-kernel {
> + qcom,entry-name = "slave-kernel";
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> + };
> +
> + smp2p-modem {
> + compatible = "qcom,smp2p";
> + qcom,smem = <435>, <428>;
> + interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
> + IPCC_MPROC_SIGNAL_SMP2P
> + IRQ_TYPE_EDGE_RISING>;
> + mboxes = <&ipcc IPCC_CLIENT_MPSS
> + IPCC_MPROC_SIGNAL_SMP2P>;
> +
> + qcom,local-pid = <0>;
> + qcom,remote-pid = <1>;
> +
> + smp2p_modem_out: master-kernel {
> + qcom,entry-name = "master-kernel";
> + #qcom,smem-state-cells = <1>;
> + };
> +
> + smp2p_modem_in: slave-kernel {
> + qcom,entry-name = "slave-kernel";
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> +
> + ipa_smp2p_out: ipa-ap-to-modem {
> + qcom,entry-name = "ipa";
> + #qcom,smem-state-cells = <1>;
> + };
> +
> + ipa_smp2p_in: ipa-modem-to-ap {
> + qcom,entry-name = "ipa";
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> + };
> +
> + smp2p-slpi {
> + compatible = "qcom,smp2p";
> + qcom,smem = <481>, <430>;
> + interrupts-extended = <&ipcc IPCC_CLIENT_SLPI
> + IPCC_MPROC_SIGNAL_SMP2P
> + IRQ_TYPE_EDGE_RISING>;
> + mboxes = <&ipcc IPCC_CLIENT_SLPI
> + IPCC_MPROC_SIGNAL_SMP2P>;
> +
> + qcom,local-pid = <0>;
> + qcom,remote-pid = <3>;
> +
> + smp2p_slpi_out: master-kernel {
> + qcom,entry-name = "master-kernel";
> + #qcom,smem-state-cells = <1>;
> + };
> +
> + smp2p_slpi_in: slave-kernel {
> + qcom,entry-name = "slave-kernel";
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> + };
> +
> soc: soc@0 {
> #address-cells = <2>;
> #size-cells = <2>;
> @@ -672,6 +789,167 @@ usb_1_ssphy: phy@...9200 {
> };
> };
>
> + remoteproc_slpi: remoteproc@...0000 {
> + compatible = "qcom,sm8350-slpi-pas";
I think this should be sm8450-slpi-pas.
Otherwise:
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@...aro.org>
> + reg = <0 0x02400000 0 0x4000>;
> +
> + interrupts-extended = <&pdc 9 IRQ_TYPE_LEVEL_HIGH>,
> + <&smp2p_slpi_in 0 IRQ_TYPE_EDGE_RISING>,
> + <&smp2p_slpi_in 1 IRQ_TYPE_EDGE_RISING>,
> + <&smp2p_slpi_in 2 IRQ_TYPE_EDGE_RISING>,
> + <&smp2p_slpi_in 3 IRQ_TYPE_EDGE_RISING>;
> + interrupt-names = "wdog", "fatal", "ready",
> + "handover", "stop-ack";
> +
> + clocks = <&rpmhcc RPMH_CXO_CLK>;
> + clock-names = "xo";
> +
> + power-domains = <&rpmhpd SM8450_LCX>,
> + <&rpmhpd SM8450_LMX>;
> + power-domain-names = "lcx", "lmx";
> +
> + memory-region = <&slpi_mem>;
> +
> + qcom,qmp = <&aoss_qmp>;
> +
> + qcom,smem-states = <&smp2p_slpi_out 0>;
> + qcom,smem-state-names = "stop";
> +
> + status = "disabled";
> +
> + glink-edge {
> + interrupts-extended = <&ipcc IPCC_CLIENT_SLPI
> + IPCC_MPROC_SIGNAL_GLINK_QMP
> + IRQ_TYPE_EDGE_RISING>;
> + mboxes = <&ipcc IPCC_CLIENT_SLPI
> + IPCC_MPROC_SIGNAL_GLINK_QMP>;
> +
> + label = "slpi";
> + qcom,remote-pid = <3>;
> + };
> + };
> +
> + remoteproc_adsp: remoteproc@...00000 {
> + compatible = "qcom,sm8450-adsp-pas";
> + reg = <0 0x030000000 0 0x100>;
> +
> + interrupts-extended = <&pdc 6 IRQ_TYPE_LEVEL_HIGH>,
> + <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
> + <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>,
> + <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>,
> + <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>;
> + interrupt-names = "wdog", "fatal", "ready",
> + "handover", "stop-ack";
> +
> + clocks = <&rpmhcc RPMH_CXO_CLK>;
> + clock-names = "xo";
> +
> + power-domains = <&rpmhpd SM8450_LCX>,
> + <&rpmhpd SM8450_LMX>;
> + power-domain-names = "lcx", "lmx";
> +
> + memory-region = <&adsp_mem>;
> +
> + qcom,qmp = <&aoss_qmp>;
> +
> + qcom,smem-states = <&smp2p_adsp_out 0>;
> + qcom,smem-state-names = "stop";
> +
> + status = "disabled";
> +
> + remoteproc_adsp_glink: glink-edge {
> + interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
> + IPCC_MPROC_SIGNAL_GLINK_QMP
> + IRQ_TYPE_EDGE_RISING>;
> + mboxes = <&ipcc IPCC_CLIENT_LPASS
> + IPCC_MPROC_SIGNAL_GLINK_QMP>;
> +
> + label = "lpass";
> + qcom,remote-pid = <2>;
> + };
> + };
> +
> + remoteproc_cdsp: remoteproc@...00000 {
> + compatible = "qcom,sm8450-cdsp-pas";
> + reg = <0 0x032300000 0 0x1400000>;
> +
> + interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_LEVEL_HIGH>,
> + <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>,
> + <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>,
> + <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>,
> + <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>;
> + interrupt-names = "wdog", "fatal", "ready",
> + "handover", "stop-ack";
> +
> + clocks = <&rpmhcc RPMH_CXO_CLK>;
> + clock-names = "xo";
> +
> + power-domains = <&rpmhpd SM8450_CX>,
> + <&rpmhpd SM8450_MXC>;
> + power-domain-names = "cx", "mxc";
> +
> + memory-region = <&cdsp_mem>;
> +
> + qcom,qmp = <&aoss_qmp>;
> +
> + qcom,smem-states = <&smp2p_cdsp_out 0>;
> + qcom,smem-state-names = "stop";
> +
> + status = "disabled";
> +
> + glink-edge {
> + interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
> + IPCC_MPROC_SIGNAL_GLINK_QMP
> + IRQ_TYPE_EDGE_RISING>;
> + mboxes = <&ipcc IPCC_CLIENT_CDSP
> + IPCC_MPROC_SIGNAL_GLINK_QMP>;
> +
> + label = "cdsp";
> + qcom,remote-pid = <5>;
> + };
> + };
> +
> + remoteproc_mpss: remoteproc@...0000 {
> + compatible = "qcom,sm8450-mpss-pas";
> + reg = <0x0 0x04080000 0x0 0x4040>;
> +
> + interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>,
> + <&smp2p_modem_in 0 IRQ_TYPE_EDGE_RISING>,
> + <&smp2p_modem_in 1 IRQ_TYPE_EDGE_RISING>,
> + <&smp2p_modem_in 2 IRQ_TYPE_EDGE_RISING>,
> + <&smp2p_modem_in 3 IRQ_TYPE_EDGE_RISING>,
> + <&smp2p_modem_in 7 IRQ_TYPE_EDGE_RISING>;
> + interrupt-names = "wdog", "fatal", "ready", "handover",
> + "stop-ack", "shutdown-ack";
> +
> + clocks = <&rpmhcc RPMH_CXO_CLK>;
> + clock-names = "xo";
> +
> + power-domains = <&rpmhpd 0>,
> + <&rpmhpd 12>;
> + power-domain-names = "cx", "mss";
> +
> + memory-region = <&mpss_mem>;
> +
> + qcom,qmp = <&aoss_qmp>;
> +
> + qcom,smem-states = <&smp2p_modem_out 0>;
> + qcom,smem-state-names = "stop";
> +
> + status = "disabled";
> +
> + glink-edge {
> + interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
> + IPCC_MPROC_SIGNAL_GLINK_QMP
> + IRQ_TYPE_EDGE_RISING>;
> + mboxes = <&ipcc IPCC_CLIENT_MPSS
> + IPCC_MPROC_SIGNAL_GLINK_QMP>;
> + interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>;
> + label = "modem";
> + qcom,remote-pid = <1>;
> + };
> + };
> +
> pdc: interrupt-controller@...0000 {
> compatible = "qcom,sm8450-pdc", "qcom,pdc";
> reg = <0 0x0b220000 0 0x30000>, <0 0x174000f0 0 0x64>;
> @@ -682,6 +960,25 @@ pdc: interrupt-controller@...0000 {
> interrupt-controller;
> };
>
> + aoss_qmp: power-controller@...0000 {
> + compatible = "qcom,sm8450-aoss-qmp", "qcom,aoss-qmp";
> + reg = <0 0x0c300000 0 0x400>;
> + interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP
> + IRQ_TYPE_EDGE_RISING>;
> + mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>;
> +
> + #clock-cells = <0>;
> + };
> +
> + ipcc: mailbox@...8000 {
> + compatible = "qcom,sm8450-ipcc", "qcom,ipcc";
> + reg = <0 0x0ed18000 0 0x1000>;
> + interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-controller;
> + #interrupt-cells = <3>;
> + #mbox-cells = <2>;
> + };
> +
> tlmm: pinctrl@...0000 {
> compatible = "qcom,sm8450-tlmm";
> reg = <0 0x0f100000 0 0x300000>;
> --
> 2.33.1
>
--
With best wishes
Dmitry
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