linux-kernel - Re: [PATCH v4,4/5] soc: mediatek: add MTK mutex support for MT8186

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Message-ID: <9d1f87ea-7db5-f22d-7f4b-8f8eb2b9985d@gmail.com>
Date:   Mon, 28 Feb 2022 12:20:34 +0100
From:   Matthias Brugger <matthias.bgg@...il.com>
To:     Rex-BC Chen <rex-bc.chen@...iatek.com>, chunkuang.hu@...nel.org,
        robh+dt@...nel.org
Cc:     p.zabel@...gutronix.de, airlied@...ux.ie, daniel@...ll.ch,
        jassisinghbrar@...il.com, fparent@...libre.com,
        yongqiang.niu@...iatek.com, hsinyi@...omium.org,
        devicetree@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
        linux-mediatek@...ts.infradead.org, linux-kernel@...r.kernel.org,
        dri-devel@...ts.freedesktop.org,
        Project_Global_Chrome_Upstream_Group@...iatek.com
Subject: Re: [PATCH v4,4/5] soc: mediatek: add MTK mutex support for MT8186



On 22/02/2022 06:28, Rex-BC Chen wrote:
> From: Yongqiang Niu <yongqiang.niu@...iatek.com>
> 
> Add MTK mutex support for MT8186 SoC.
> We need MTK mutex to control timing of display modules and there
> are two display pipelines for MT8186 including internal and external
> display.
> 
> MTK mutex for internal display:
> - Timing source: DSI
> - Control modules: OVL0/RDMA0/COLOR0/CCORR/AAL0/GAMMA/POSTMASK0/DITHER
> 
> MTK mutex for external display:
> - Timing source : DPI
> - Control modules: OVL_2L0/RDMA1
> 
> Signed-off-by: Yongqiang Niu <yongqiang.niu@...iatek.com>
> Signed-off-by: Rex-BC Chen <rex-bc.chen@...iatek.com>

applied thanks

> ---
>   drivers/soc/mediatek/mtk-mutex.c | 45 ++++++++++++++++++++++++++++++++
>   1 file changed, 45 insertions(+)
> 
> diff --git a/drivers/soc/mediatek/mtk-mutex.c b/drivers/soc/mediatek/mtk-mutex.c
> index 2ca55bb5a8be..aaf8fc1abb43 100644
> --- a/drivers/soc/mediatek/mtk-mutex.c
> +++ b/drivers/soc/mediatek/mtk-mutex.c
> @@ -26,6 +26,23 @@
>   
>   #define INT_MUTEX				BIT(1)
>   
> +#define MT8186_MUTEX_MOD_DISP_OVL0		0
> +#define MT8186_MUTEX_MOD_DISP_OVL0_2L		1
> +#define MT8186_MUTEX_MOD_DISP_RDMA0		2
> +#define MT8186_MUTEX_MOD_DISP_COLOR0		4
> +#define MT8186_MUTEX_MOD_DISP_CCORR0		5
> +#define MT8186_MUTEX_MOD_DISP_AAL0		7
> +#define MT8186_MUTEX_MOD_DISP_GAMMA0		8
> +#define MT8186_MUTEX_MOD_DISP_POSTMASK0		9
> +#define MT8186_MUTEX_MOD_DISP_DITHER0		10
> +#define MT8186_MUTEX_MOD_DISP_RDMA1		17
> +
> +#define MT8186_MUTEX_SOF_SINGLE_MODE		0
> +#define MT8186_MUTEX_SOF_DSI0			1
> +#define MT8186_MUTEX_SOF_DPI0			2
> +#define MT8186_MUTEX_EOF_DSI0			(MT8186_MUTEX_SOF_DSI0 << 6)
> +#define MT8186_MUTEX_EOF_DPI0			(MT8186_MUTEX_SOF_DPI0 << 6)
> +
>   #define MT8167_MUTEX_MOD_DISP_PWM		1
>   #define MT8167_MUTEX_MOD_DISP_OVL0		6
>   #define MT8167_MUTEX_MOD_DISP_OVL1		7
> @@ -226,6 +243,19 @@ static const unsigned int mt8183_mutex_mod[DDP_COMPONENT_ID_MAX] = {
>   	[DDP_COMPONENT_WDMA0] = MT8183_MUTEX_MOD_DISP_WDMA0,
>   };
>   
> +static const unsigned int mt8186_mutex_mod[DDP_COMPONENT_ID_MAX] = {
> +	[DDP_COMPONENT_AAL0] = MT8186_MUTEX_MOD_DISP_AAL0,
> +	[DDP_COMPONENT_CCORR] = MT8186_MUTEX_MOD_DISP_CCORR0,
> +	[DDP_COMPONENT_COLOR0] = MT8186_MUTEX_MOD_DISP_COLOR0,
> +	[DDP_COMPONENT_DITHER] = MT8186_MUTEX_MOD_DISP_DITHER0,
> +	[DDP_COMPONENT_GAMMA] = MT8186_MUTEX_MOD_DISP_GAMMA0,
> +	[DDP_COMPONENT_OVL0] = MT8186_MUTEX_MOD_DISP_OVL0,
> +	[DDP_COMPONENT_OVL_2L0] = MT8186_MUTEX_MOD_DISP_OVL0_2L,
> +	[DDP_COMPONENT_POSTMASK0] = MT8186_MUTEX_MOD_DISP_POSTMASK0,
> +	[DDP_COMPONENT_RDMA0] = MT8186_MUTEX_MOD_DISP_RDMA0,
> +	[DDP_COMPONENT_RDMA1] = MT8186_MUTEX_MOD_DISP_RDMA1,
> +};
> +
>   static const unsigned int mt8192_mutex_mod[DDP_COMPONENT_ID_MAX] = {
>   	[DDP_COMPONENT_AAL0] = MT8192_MUTEX_MOD_DISP_AAL0,
>   	[DDP_COMPONENT_CCORR] = MT8192_MUTEX_MOD_DISP_CCORR0,
> @@ -264,6 +294,12 @@ static const unsigned int mt8183_mutex_sof[MUTEX_SOF_DSI3 + 1] = {
>   	[MUTEX_SOF_DPI0] = MT8183_MUTEX_SOF_DPI0 | MT8183_MUTEX_EOF_DPI0,
>   };
>   
> +static const unsigned int mt8186_mutex_sof[MUTEX_SOF_DSI3 + 1] = {
> +	[MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE,
> +	[MUTEX_SOF_DSI0] = MT8186_MUTEX_SOF_DSI0 | MT8186_MUTEX_EOF_DSI0,
> +	[MUTEX_SOF_DPI0] = MT8186_MUTEX_SOF_DPI0 | MT8186_MUTEX_EOF_DPI0,
> +};
> +
>   static const struct mtk_mutex_data mt2701_mutex_driver_data = {
>   	.mutex_mod = mt2701_mutex_mod,
>   	.mutex_sof = mt2712_mutex_sof,
> @@ -301,6 +337,13 @@ static const struct mtk_mutex_data mt8183_mutex_driver_data = {
>   	.no_clk = true,
>   };
>   
> +static const struct mtk_mutex_data mt8186_mutex_driver_data = {
> +	.mutex_mod = mt8186_mutex_mod,
> +	.mutex_sof = mt8186_mutex_sof,
> +	.mutex_mod_reg = MT8183_MUTEX0_MOD0,
> +	.mutex_sof_reg = MT8183_MUTEX0_SOF0,
> +};
> +
>   static const struct mtk_mutex_data mt8192_mutex_driver_data = {
>   	.mutex_mod = mt8192_mutex_mod,
>   	.mutex_sof = mt8183_mutex_sof,
> @@ -540,6 +583,8 @@ static const struct of_device_id mutex_driver_dt_match[] = {
>   	  .data = &mt8173_mutex_driver_data},
>   	{ .compatible = "mediatek,mt8183-disp-mutex",
>   	  .data = &mt8183_mutex_driver_data},
> +	{ .compatible = "mediatek,mt8186-disp-mutex",
> +	  .data = &mt8186_mutex_driver_data},
>   	{ .compatible = "mediatek,mt8192-disp-mutex",
>   	  .data = &mt8192_mutex_driver_data},
>   	{},