lists.openwall.net | lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC | |
Open Source and information security mailing list archives
| ||
|
Date: Tue, 01 Mar 2022 10:11:34 -0000 From: "irqchip-bot for Marc Zyngier" <tip-bot2@...utronix.de> To: linux-kernel@...r.kernel.org Cc: Marc Zyngier <maz@...nel.org>, Maulik Shah <quic_mkshah@...cinc.com>, tglx@...utronix.de Subject: [irqchip: irq/irqchip-next] irqchip/qcom-pdc: Fix broken locking The following commit has been merged into the irq/irqchip-next branch of irqchip: Commit-ID: a6aca2f460e203781dc41391913cc5b54f4bc0ce Gitweb: https://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms/a6aca2f460e203781dc41391913cc5b54f4bc0ce Author: Marc Zyngier <maz@...nel.org> AuthorDate: Thu, 24 Feb 2022 10:12:25 Committer: Marc Zyngier <maz@...nel.org> CommitterDate: Tue, 01 Mar 2022 10:06:25 irqchip/qcom-pdc: Fix broken locking pdc_enable_intr() serves as a primitive to qcom_pdc_gic_{en,dis}able, and has a raw spinlock for mutual exclusion, which is uses with interruptible primitives. This means that this critical section can itself be interrupted. Should the interrupt also be a PDC interrupt, and the endpoint driver perform an irq_disable() on that interrupt, we end-up in a deadlock. Fix this by using the irqsave/irqrestore variants of the locking primitives. Signed-off-by: Marc Zyngier <maz@...nel.org> Reviewed-by: Maulik Shah <quic_mkshah@...cinc.com> Link: https://lore.kernel.org/r/20220224101226.88373-5-maz@kernel.org --- drivers/irqchip/qcom-pdc.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/irqchip/qcom-pdc.c b/drivers/irqchip/qcom-pdc.c index 837ca69..0cd20dd 100644 --- a/drivers/irqchip/qcom-pdc.c +++ b/drivers/irqchip/qcom-pdc.c @@ -55,17 +55,18 @@ static u32 pdc_reg_read(int reg, u32 i) static void pdc_enable_intr(struct irq_data *d, bool on) { int pin_out = d->hwirq; + unsigned long flags; u32 index, mask; u32 enable; index = pin_out / 32; mask = pin_out % 32; - raw_spin_lock(&pdc_lock); + raw_spin_lock_irqsave(&pdc_lock, flags); enable = pdc_reg_read(IRQ_ENABLE_BANK, index); enable = on ? ENABLE_INTR(enable, mask) : CLEAR_INTR(enable, mask); pdc_reg_write(IRQ_ENABLE_BANK, index, enable); - raw_spin_unlock(&pdc_lock); + raw_spin_unlock_irqrestore(&pdc_lock, flags); } static void qcom_pdc_gic_disable(struct irq_data *d)
Powered by blists - more mailing lists