linux-kernel - Re: [PATCH v2 5/7] PCI: qcom: Add SM8150 SoC support

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Date:   Tue, 1 Mar 2022 14:43:50 +0300
From:   Dmitry Baryshkov <dmitry.baryshkov@...aro.org>
To:     Bhupesh Sharma <bhupesh.sharma@...aro.org>,
        linux-arm-msm@...r.kernel.org, linux-pci@...r.kernel.org,
        devicetree@...r.kernel.org
Cc:     bhupesh.linux@...il.com, lorenzo.pieralisi@....com,
        agross@...nel.org, bjorn.andersson@...aro.org,
        svarbanov@...sol.com, bhelgaas@...gle.com,
        linux-kernel@...r.kernel.org, robh+dt@...nel.org, sboyd@...nel.org,
        mturquette@...libre.com, linux-clk@...r.kernel.org,
        Vinod Koul <vkoul@...nel.org>
Subject: Re: [PATCH v2 5/7] PCI: qcom: Add SM8150 SoC support

On 01/03/2022 10:25, Bhupesh Sharma wrote:
> The PCIe IP (rev 1.5.0) on SM8150 SoC is similar to the one used on
> SM8250. Hence the support is added reusing the members of ops_2_7_0.
> 
> Cc: Vinod Koul <vkoul@...nel.org>
> Cc: Rob Herring <robh+dt@...nel.org>
> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@...aro.org>
> Signed-off-by: Bhupesh Sharma <bhupesh.sharma@...aro.org>
> ---
>   drivers/pci/controller/dwc/pcie-qcom.c | 16 ++++++++++++++++
>   1 file changed, 16 insertions(+)
> 
> diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c
> index c19cd506ed3f..66fbc0234888 100644
> --- a/drivers/pci/controller/dwc/pcie-qcom.c
> +++ b/drivers/pci/controller/dwc/pcie-qcom.c
> @@ -1487,6 +1487,17 @@ static const struct qcom_pcie_ops ops_1_9_0 = {
>   	.config_sid = qcom_pcie_config_sid_sm8250,
>   };
>   
> +/* Qcom IP rev.: 1.5.0 */
> +static const struct qcom_pcie_ops ops_1_5_0 = {
> +	.get_resources = qcom_pcie_get_resources_2_7_0,
> +	.init = qcom_pcie_init_2_7_0,
> +	.deinit = qcom_pcie_deinit_2_7_0,
> +	.ltssm_enable = qcom_pcie_2_3_2_ltssm_enable,
> +	.post_init = qcom_pcie_post_init_2_7_0,
> +	.post_deinit = qcom_pcie_post_deinit_2_7_0,
> +	.config_sid = qcom_pcie_config_sid_sm8250,
> +};
> +

This duplicates the ops_1_9_0, doesn't it?
I'd suggest to reuse 1.9.0 structure and add a comment that it's also 
used for 1.5.0.

>   static const struct qcom_pcie_cfg apq8084_cfg = {
>   	.ops = &ops_1_0_0,
>   };
> @@ -1511,6 +1522,10 @@ static const struct qcom_pcie_cfg sdm845_cfg = {
>   	.ops = &ops_2_7_0,
>   };
>   
> +static const struct qcom_pcie_cfg sm8150_cfg = {
> +	.ops = &ops_1_5_0,
> +};
> +
>   static const struct qcom_pcie_cfg sm8250_cfg = {
>   	.ops = &ops_1_9_0,
>   };
> @@ -1626,6 +1641,7 @@ static const struct of_device_id qcom_pcie_match[] = {
>   	{ .compatible = "qcom,pcie-ipq4019", .data = &ipq4019_cfg },
>   	{ .compatible = "qcom,pcie-qcs404", .data = &ipq4019_cfg },
>   	{ .compatible = "qcom,pcie-sdm845", .data = &sdm845_cfg },
> +	{ .compatible = "qcom,pcie-sm8150", .data = &sm8150_cfg },
>   	{ .compatible = "qcom,pcie-sm8250", .data = &sm8250_cfg },
>   	{ .compatible = "qcom,pcie-sc8180x", .data = &sm8250_cfg },
>   	{ .compatible = "qcom,pcie-sc7280", .data = &sc7280_cfg },


-- 
With best wishes
Dmitry