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Message-ID: <CAEyMn7aTKTguzEd-UNNb+-a30t5YBzkhXXBEKL360q10x-t9vg@mail.gmail.com>
Date: Tue, 1 Mar 2022 17:12:33 +0100
From: Heiko Thiery <heiko.thiery@...il.com>
To: Michael Walle <michael@...le.cc>
Cc: Rob Herring <robh+dt@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski@...onical.com>,
Shawn Guo <shawnguo@...nel.org>,
Sascha Hauer <s.hauer@...gutronix.de>,
Fabio Estevam <festevam@...il.com>,
Pengutronix Kernel Team <kernel@...gutronix.de>,
NXP Linux Team <linux-imx@....com>,
devicetree@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
linux-kernel@...r.kernel.org
Subject: Re: [PATCH] arm64: dts: imx8mn-evk: add QSPI flash
Hi Michael
Am Mo., 28. Feb. 2022 um 14:25 Uhr schrieb Michael Walle <michael@...le.cc>:
>
> There is a 32MiB Micron MT25QU256ABA1 serial NOR flash on the EVK board.
> Add a device tree node for it.
>
> Tested on a 8MNANOD3L-EVK.
>
> Signed-off-by: Michael Walle <michael@...le.cc>
Tested-by: Heiko Thiery <heiko.thiery@...il.com>
> ---
> arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi | 27 +++++++++++++++++++
> 1 file changed, 27 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi b/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi
> index c3f15192b76c..dc75d6d13bb3 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi
> @@ -110,6 +110,22 @@ vddio: vddio-regulator {
> };
> };
>
> +&flexspi {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_flexspi>;
> + status = "okay";
> +
> + flash0: flash@0 {
> + compatible = "jedec,spi-nor";
> + reg = <0>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> + spi-max-frequency = <166000000>;
> + spi-tx-bus-width = <4>;
> + spi-rx-bus-width = <4>;
> + };
> +};
> +
> &i2c1 {
> clock-frequency = <400000>;
> pinctrl-names = "default";
> @@ -267,6 +283,17 @@ MX8MN_IOMUXC_SAI2_RXC_GPIO4_IO22 0x19
> >;
> };
>
> + pinctrl_flexspi: flexspigrp {
> + fsl,pins = <
> + MX8MN_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x1c2
> + MX8MN_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82
> + MX8MN_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x82
> + MX8MN_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x82
> + MX8MN_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x82
> + MX8MN_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x82
> + >;
> + };
> +
> pinctrl_gpio_led: gpioledgrp {
> fsl,pins = <
> MX8MN_IOMUXC_NAND_READY_B_GPIO3_IO16 0x19
> --
> 2.30.2
>
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