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Message-ID: <CACPK8XcsLBrJo7W5y3sE_jGy9j4e6MPNcB26bJ4SB1ZhVuka+A@mail.gmail.com>
Date: Wed, 2 Mar 2022 03:08:22 +0000
From: Joel Stanley <joel@....id.au>
To: Tommy Haung <tommy_huang@...eedtech.com>
Cc: David Airlie <airlied@...ux.ie>, Daniel Vetter <daniel@...ll.ch>,
Rob Herring <robh+dt@...nel.org>,
Andrew Jeffery <andrew@...id.au>,
linux-aspeed <linux-aspeed@...ts.ozlabs.org>,
"open list:DRM DRIVERS" <dri-devel@...ts.freedesktop.org>,
devicetree <devicetree@...r.kernel.org>,
Linux ARM <linux-arm-kernel@...ts.infradead.org>,
Linux Kernel Mailing List <linux-kernel@...r.kernel.org>,
BMC-SW <BMC-SW@...eedtech.com>
Subject: Re: [PATCH v6 5/5] ARM: dtsi: aspeed: Modified gfx reset control
On Wed, 2 Mar 2022 at 02:50, Tommy Haung <tommy_huang@...eedtech.com> wrote:
>
> Remove the ast2500-gfx from aspeed-g6.dtsi.
> In the AST2600, the ASPEED_RESET_CRT1 is replaced by
> ASPEED_RESET_GRAPHICS. This is no differnce between these two reset
> behavior but reigster location is changed. The HW controller states
> and FW programming resgiter will be reset by CRT reset controller bit
> (SCU040[13]). And another part HW controller will be reset by
> Graphics controller bit (SCU040[26]). These two reset bit need be
> de-assert then the SOC display will be active.
>
> Signed-off-by: Tommy Haung <tommy_huang@...eedtech.com>
You don't need this patch; the change should be part of the patch that
introduces the node. I'll fix that up when applying.
> ---
> arch/arm/boot/dts/aspeed-g6.dtsi | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/arm/boot/dts/aspeed-g6.dtsi b/arch/arm/boot/dts/aspeed-g6.dtsi
> index e38c3742761b..7cc99bc68558 100644
> --- a/arch/arm/boot/dts/aspeed-g6.dtsi
> +++ b/arch/arm/boot/dts/aspeed-g6.dtsi
> @@ -352,7 +352,7 @@
> };
>
> gfx: display@...e6000 {
> - compatible = "aspeed,ast2600-gfx", "aspeed,ast2500-gfx", "syscon";
> + compatible = "aspeed,ast2600-gfx", "syscon";
> reg = <0x1e6e6000 0x1000>;
> reg-io-width = <4>;
> clocks = <&syscon ASPEED_CLK_GATE_D1CLK>;
> --
> 2.17.1
>
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