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Message-ID: <CAA8EJpqEy+669gpDsy-zGp2NpDP-d7ZxNf7RVo=OQZdvGdZOvQ@mail.gmail.com>
Date: Wed, 2 Mar 2022 23:59:27 +0300
From: Dmitry Baryshkov <dmitry.baryshkov@...aro.org>
To: Bhupesh Sharma <bhupesh.sharma@...aro.org>
Cc: linux-arm-msm@...r.kernel.org, linux-pci@...r.kernel.org,
devicetree@...r.kernel.org, bhupesh.linux@...il.com,
lorenzo.pieralisi@....com, agross@...nel.org,
bjorn.andersson@...aro.org, svarbanov@...sol.com,
bhelgaas@...gle.com, linux-kernel@...r.kernel.org,
robh+dt@...nel.org, sboyd@...nel.org, mturquette@...libre.com,
linux-clk@...r.kernel.org, Vinod Koul <vkoul@...nel.org>
Subject: Re: [PATCH v3 7/7] arm64: dts: qcom: sa8155: Enable PCIe nodes
On Wed, 2 Mar 2022 at 23:31, Bhupesh Sharma <bhupesh.sharma@...aro.org> wrote:
>
> SA8155p ADP board supports the PCIe0 controller in the RC
> mode (only). So add the support for the same.
>
> Cc: Bjorn Andersson <bjorn.andersson@...aro.org>
> Cc: Vinod Koul <vkoul@...nel.org>
> Cc: Rob Herring <robh+dt@...nel.org>
> Signed-off-by: Bhupesh Sharma <bhupesh.sharma@...aro.org>
> ---
> arch/arm64/boot/dts/qcom/sa8155p-adp.dts | 42 ++++++++++++++++++++++++
> 1 file changed, 42 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/sa8155p-adp.dts b/arch/arm64/boot/dts/qcom/sa8155p-adp.dts
> index 8756c2b25c7e..3f6b3ee404f5 100644
> --- a/arch/arm64/boot/dts/qcom/sa8155p-adp.dts
> +++ b/arch/arm64/boot/dts/qcom/sa8155p-adp.dts
> @@ -387,9 +387,51 @@ &usb_2_qmpphy {
> vdda-pll-supply = <&vdda_usb_ss_dp_core_1>;
> };
>
> +&pcie0 {
> + status = "okay";
> +};
> +
> +&pcie0_phy {
> + status = "okay";
> + vdda-phy-supply = <&vreg_l18c_0p88>;
> + vdda-pll-supply = <&vreg_l8c_1p2>;
> +};
> +
> +&pcie1_phy {
> + vdda-phy-supply = <&vreg_l18c_0p88>;
> + vdda-pll-supply = <&vreg_l8c_1p2>;
> +};
> +
> &tlmm {
> gpio-reserved-ranges = <0 4>;
>
> + bt_en_default: bt_en_default {
> + mux {
> + pins = "gpio172";
> + function = "gpio";
> + };
> +
> + config {
> + pins = "gpio172";
> + drive-strength = <2>;
> + bias-pull-down;
> + };
> + };
> +
> + wlan_en_default: wlan_en_default {
> + mux {
> + pins = "gpio169";
> + function = "gpio";
> + };
> +
> + config {
> + pins = "gpio169";
> + drive-strength = <16>;
> + output-high;
> + bias-pull-up;
> + };
> + };
> +
Not related to PCIe
> usb2phy_ac_en1_default: usb2phy_ac_en1_default {
> mux {
> pins = "gpio113";
> --
> 2.35.1
>
--
With best wishes
Dmitry
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