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Message-ID: <20220302064556.GA18820@gao-cwp>
Date: Wed, 2 Mar 2022 14:45:57 +0800
From: Chao Gao <chao.gao@...el.com>
To: Maxim Levitsky <mlevitsk@...hat.com>
Cc: Zeng Guang <guang.zeng@...el.com>,
Paolo Bonzini <pbonzini@...hat.com>,
Sean Christopherson <seanjc@...gle.com>,
Vitaly Kuznetsov <vkuznets@...hat.com>,
Wanpeng Li <wanpengli@...cent.com>,
Jim Mattson <jmattson@...gle.com>,
Joerg Roedel <joro@...tes.org>, kvm@...r.kernel.org,
Dave Hansen <dave.hansen@...ux.intel.com>,
Tony Luck <tony.luck@...el.com>,
Kan Liang <kan.liang@...ux.intel.com>,
Thomas Gleixner <tglx@...utronix.de>,
Ingo Molnar <mingo@...hat.com>, Borislav Petkov <bp@...en8.de>,
"H. Peter Anvin" <hpa@...or.com>,
Kim Phillips <kim.phillips@....com>,
Jarkko Sakkinen <jarkko@...nel.org>,
Jethro Beekman <jethro@...tanix.com>,
Kai Huang <kai.huang@...el.com>, x86@...nel.org,
linux-kernel@...r.kernel.org, Robert Hu <robert.hu@...el.com>
Subject: Re: [PATCH v6 7/9] KVM: VMX: enable IPI virtualization
>>> static void init_vmcs(struct vcpu_vmx *vmx)
>>> {
>>> + struct kvm_vcpu *vcpu = &vmx->vcpu;
>>> + struct kvm_vmx *kvm_vmx = to_kvm_vmx(vcpu->kvm);
>>> +
>>> if (nested)
>>> nested_vmx_set_vmcs_shadowing_bitmap();
>>>
>>> @@ -4431,7 +4460,7 @@ static void init_vmcs(struct vcpu_vmx *vmx)
>>> if (cpu_has_tertiary_exec_ctrls())
>>> tertiary_exec_controls_set(vmx, vmx_tertiary_exec_control(vmx));
>>>
>>> - if (kvm_vcpu_apicv_active(&vmx->vcpu)) {
>>> + if (kvm_vcpu_apicv_active(vcpu)) {
>>
>>here too (pre-existing), I also not 100% sure that kvm_vcpu_apicv_active
>>should be used. I haven't studied APICv code that much to be 100% sure.
>
On second thoughts, I think you are correct. Below VMCS fields
(i.e, EIO_EXIT_BITMAP0/1/2, POSTED_INTR_NV/DESC_ADDR) should be configured as
long as the VM can enable APICv, particularly considering
vmx_refresh_apicv_exec_ctrl() doesn't configure these VMCS fields when APICv
gets activated.
This is a latent bug in KVM. We will fix it with a separate patch.
>I think kvm_vcpu_apicv_active is better.
>
>The question is: If CPU supports a VMX feature (APICv), but it isn't enabled
>now, is it allowed to configure VMCS fields defined by the feature? Would CPU
>ignore the values written to the fields or retain them after enabling the
>feature later?
This concern is invalid. SDM doesn't mention any ordering requirement about
configuring a feature's vm-execution bit and other VMCS fields introduced for
the feature. Please disregard my original remark.
>
>Personally, KVM shouldn't rely on CPU's behavior in this case. So, It is better
>for KVM to write below VMCS fields only if APICv is enabled.
>
>>
>>
>>> vmcs_write64(EOI_EXIT_BITMAP0, 0);
>>> vmcs_write64(EOI_EXIT_BITMAP1, 0);
>>> vmcs_write64(EOI_EXIT_BITMAP2, 0);
>>> @@ -4441,6 +4470,13 @@ static void init_vmcs(struct vcpu_vmx *vmx)
>>>
>>> vmcs_write16(POSTED_INTR_NV, POSTED_INTR_VECTOR);
>>> vmcs_write64(POSTED_INTR_DESC_ADDR, __pa((&vmx->pi_desc)));
>>> +
>>> + if (enable_ipiv) {
>>> + WRITE_ONCE(kvm_vmx->pid_table[vcpu->vcpu_id],
>>> + __pa(&vmx->pi_desc) | PID_TABLE_ENTRY_VALID);
>>> + vmcs_write64(PID_POINTER_TABLE, __pa(kvm_vmx->pid_table));
>>> + vmcs_write16(LAST_PID_POINTER_INDEX, kvm_vmx->pid_last_index);
>>> + }
>>> }
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