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Message-ID: <1646210609-21943-3-git-send-email-amhetre@nvidia.com>
Date: Wed, 2 Mar 2022 14:13:27 +0530
From: Ashish Mhetre <amhetre@...dia.com>
To: <robh+dt@...nel.org>, <krzysztof.kozlowski@...onical.com>,
<thierry.reding@...il.com>, <jonathanh@...dia.com>,
<digetx@...il.com>, <linux-kernel@...r.kernel.org>,
<devicetree@...r.kernel.org>, <linux-tegra@...r.kernel.org>
CC: <vdumpa@...dia.com>, <Snikam@...dia.com>, <amhetre@...dia.com>
Subject: [Patch v4 2/4] dt-bindings: memory: Update reg maxitems for tegra186
>From tegra186 onwards, memory controller support multiple channels.
Reg items are updated with address and size of these channels.
Tegra186 has overall 5 memory controller channels. Tegra194 and tegra234
have overall 17 memory controller channels each.
There is 1 reg item for memory controller stream-id registers.
So update the reg maxItems to 18 in tegra186 devicetree documentation.
Signed-off-by: Ashish Mhetre <amhetre@...dia.com>
---
.../devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml
index 13c4c82..eb7ed00 100644
--- a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml
+++ b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml
@@ -35,7 +35,7 @@ properties:
reg:
minItems: 1
- maxItems: 3
+ maxItems: 18
interrupts:
items:
--
2.7.4
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