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Message-ID: <a958a934-5a24-e5c5-c4c9-ce46a2b140b6@collabora.com> Date: Wed, 2 Mar 2022 11:13:06 +0100 From: AngeloGioacchino Del Regno <angelogioacchino.delregno@...labora.com> To: "Nancy.Lin" <nancy.lin@...iatek.com>, CK Hu <ck.hu@...iatek.com> Cc: Chun-Kuang Hu <chunkuang.hu@...nel.org>, Philipp Zabel <p.zabel@...gutronix.de>, David Airlie <airlied@...ux.ie>, Daniel Vetter <daniel@...ll.ch>, Rob Herring <robh+dt@...nel.org>, Matthias Brugger <matthias.bgg@...il.com>, "jason-jh . lin" <jason-jh.lin@...iatek.com>, Yongqiang Niu <yongqiang.niu@...iatek.com>, dri-devel@...ts.freedesktop.org, linux-mediatek@...ts.infradead.org, devicetree@...r.kernel.org, linux-kernel@...r.kernel.org, linux-arm-kernel@...ts.infradead.org, singo.chang@...iatek.com, srv_heupstream@...iatek.com Subject: Re: [PATCH v12 01/23] dt-bindings: mediatek: add vdosys1 RDMA definition for mt8195 Il 22/02/22 11:07, Nancy.Lin ha scritto: > Add vdosys1 RDMA definition. > > Signed-off-by: Nancy.Lin <nancy.lin@...iatek.com> > --- > .../arm/mediatek/mediatek,mdp-rdma.yaml | 77 +++++++++++++++++++ > 1 file changed, 77 insertions(+) > create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,mdp-rdma.yaml > > diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mdp-rdma.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mdp-rdma.yaml > new file mode 100644 > index 000000000000..d70b81ec1914 > --- /dev/null > +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mdp-rdma.yaml > @@ -0,0 +1,77 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/arm/mediatek/mediatek,mdp-rdma.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Mediatek MDP RDMA > + > +maintainers: > + - Matthias Brugger <matthias.bgg@...il.com> > + > +description: | > + The mediatek MDP RDMA stands for Read Direct Memory Access. > + It provides real time data to the back-end panel driver, such as DSI, > + DPI and DP_INTF. > + It contains one line buffer to store the sufficient pixel data. > + RDMA device node must be siblings to the central MMSYS_CONFIG node. > + For a description of the MMSYS_CONFIG binding, see > + Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml for details. > + > +properties: > + compatible: > + oneOf: > + - items: > + - const: mediatek,mt8195-vdo1-rdma > + > + reg: > + maxItems: 1 > + > + interrupts: > + maxItems: 1 > + > + power-domains: > + description: A phandle and PM domain specifier as defined by bindings of > + the power controller specified by phandle. See > + Documentation/devicetree/bindings/power/power-domain.yaml for details. > + > + clocks: > + items: > + - description: RDMA Clock > + > + iommus: > + description: > + This property should point to the respective IOMMU block with master port as argument, > + see Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml for details. > + > + mediatek,gce-client-reg: > + description: > + The register of display function block to be set by gce. There are 4 arguments, > + such as gce node, subsys id, offset and register size. The subsys id that is > + mapping to the register of display function blocks is defined in the gce header > + include/include/dt-bindings/gce/<chip>-gce.h of each chips. > + $ref: /schemas/types.yaml#/definitions/phandle-array > + maxItems: 1 > + > +required: > + - compatible > + - reg > + - power-domains > + - clocks > + - iommus > + > +additionalProperties: false > + > +examples: > + - | You're missing a couple of header inclusions and relying on the default address-cells, size-cells, which is wrong here, as you have two of both. #include ......... soc { #address-cells = <2>; #size-cells = <2>; vdo1_rdma0: ....... > + > + vdo1_rdma0: vdo1_rdma@...04000 { > + compatible = "mediatek,mt8195-vdo1-rdma"; > + reg = <0 0x1c104000 0 0x1000>; > + interrupts = <GIC_SPI 495 IRQ_TYPE_LEVEL_HIGH 0>; > + clocks = <&vdosys1 CLK_VDO1_MDP_RDMA0>; > + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; > + iommus = <&iommu_vdo M4U_PORT_L2_MDP_RDMA0>; > + mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x4000 0x1000>; > + }; > +
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