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Message-ID: <243c2a77-6fbf-6afa-b773-de9b58aa4997@collabora.com>
Date: Wed, 2 Mar 2022 11:13:50 +0100
From: AngeloGioacchino Del Regno
<angelogioacchino.delregno@...labora.com>
To: "Nancy.Lin" <nancy.lin@...iatek.com>, CK Hu <ck.hu@...iatek.com>
Cc: Chun-Kuang Hu <chunkuang.hu@...nel.org>,
Philipp Zabel <p.zabel@...gutronix.de>,
David Airlie <airlied@...ux.ie>,
Daniel Vetter <daniel@...ll.ch>,
Rob Herring <robh+dt@...nel.org>,
Matthias Brugger <matthias.bgg@...il.com>,
"jason-jh . lin" <jason-jh.lin@...iatek.com>,
Yongqiang Niu <yongqiang.niu@...iatek.com>,
dri-devel@...ts.freedesktop.org,
linux-mediatek@...ts.infradead.org, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
singo.chang@...iatek.com, srv_heupstream@...iatek.com
Subject: Re: [PATCH v12 03/23] dt-bindings: mediatek: add ethdr definition for
mt8195
Il 22/02/22 11:07, Nancy.Lin ha scritto:
> Add vdosys1 ETHDR definition.
>
> Signed-off-by: Nancy.Lin <nancy.lin@...iatek.com>
> Reviewed-by: Chun-Kuang Hu <chunkuang.hu@...nel.org>
> ---
> .../display/mediatek/mediatek,ethdr.yaml | 147 ++++++++++++++++++
> 1 file changed, 147 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr.yaml
>
> diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr.yaml
> new file mode 100644
> index 000000000000..131eed5eeeb7
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr.yaml
> @@ -0,0 +1,147 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/display/mediatek/mediatek,ethdr.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Mediatek Ethdr Device Tree Bindings
> +
> +maintainers:
> + - Chun-Kuang Hu <chunkuang.hu@...nel.org>
> + - Philipp Zabel <p.zabel@...gutronix.de>
> +
> +description: |
> + ETHDR is designed for HDR video and graphics conversion in the external display path.
> + It handles multiple HDR input types and performs tone mapping, color space/color
> + format conversion, and then combine different layers, output the required HDR or
> + SDR signal to the subsequent display path. This engine is composed of two video
> + frontends, two graphic frontends, one video backend and a mixer. ETHDR has two
> + DMA function blocks, DS and ADL. These two function blocks read the pre-programmed
> + registers from DRAM and set them to HW in the v-blanking period.
> +
> +properties:
> + compatible:
> + items:
> + - const: mediatek,mt8195-disp-ethdr
> + reg:
> + maxItems: 7
> + reg-names:
> + items:
> + - const: mixer
> + - const: vdo_fe0
> + - const: vdo_fe1
> + - const: gfx_fe0
> + - const: gfx_fe1
> + - const: vdo_be
> + - const: adl_ds
> + interrupts:
> + minItems: 1
> + iommus:
> + description: The compatible property is DMA function blocks.
> + Should point to the respective IOMMU block with master port as argument,
> + see Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml for
> + details.
> + minItems: 1
> + maxItems: 2
> + clocks:
> + items:
> + - description: mixer clock
> + - description: video frontend 0 clock
> + - description: video frontend 1 clock
> + - description: graphic frontend 0 clock
> + - description: graphic frontend 1 clock
> + - description: video backend clock
> + - description: autodownload and menuload clock
> + - description: video frontend 0 async clock
> + - description: video frontend 1 async clock
> + - description: graphic frontend 0 async clock
> + - description: graphic frontend 1 async clock
> + - description: video backend async clock
> + - description: ethdr top clock
> + clock-names:
> + items:
> + - const: mixer
> + - const: vdo_fe0
> + - const: vdo_fe1
> + - const: gfx_fe0
> + - const: gfx_fe1
> + - const: vdo_be
> + - const: adl_ds
> + - const: vdo_fe0_async
> + - const: vdo_fe1_async
> + - const: gfx_fe0_async
> + - const: gfx_fe1_async
> + - const: vdo_be_async
> + - const: ethdr_top
> + power-domains:
> + maxItems: 1
> + resets:
> + maxItems: 5
> + mediatek,gce-client-reg:
> + $ref: /schemas/types.yaml#/definitions/phandle-array
> + description: The register of display function block to be set by gce.
> + There are 4 arguments in this property, gce node, subsys id, offset and
> + register size. The subsys id is defined in the gce header of each chips
> + include/include/dt-bindings/gce/<chip>-gce.h, mapping to the register of
> + display function block.
> +
> +required:
> + - compatible
> + - reg
> + - clocks
> + - clock-names
> + - interrupts
> + - power-domains
> +
> +additionalProperties: false
> +
> +examples:
> + - |
Please fix inclusions and address/size cells.
Thanks,
Angelo
> +
> + disp_ethdr@...14000 {
> + compatible = "mediatek,mt8195-disp-ethdr";
> + reg = <0 0x1c114000 0 0x1000>,
> + <0 0x1c115000 0 0x1000>,
> + <0 0x1c117000 0 0x1000>,
> + <0 0x1c119000 0 0x1000>,
> + <0 0x1c11A000 0 0x1000>,
> + <0 0x1c11B000 0 0x1000>,
> + <0 0x1c11C000 0 0x1000>;
> + reg-names = "mixer", "vdo_fe0", "vdo_fe1", "gfx_fe0", "gfx_fe1",
> + "vdo_be", "adl_ds";
> + mediatek,gce-client-reg = <&gce0 SUBSYS_1c11XXXX 0x4000 0x1000>,
> + <&gce0 SUBSYS_1c11XXXX 0x5000 0x1000>,
> + <&gce0 SUBSYS_1c11XXXX 0x7000 0x1000>,
> + <&gce0 SUBSYS_1c11XXXX 0x9000 0x1000>,
> + <&gce0 SUBSYS_1c11XXXX 0xA000 0x1000>,
> + <&gce0 SUBSYS_1c11XXXX 0xB000 0x1000>,
> + <&gce0 SUBSYS_1c11XXXX 0xC000 0x1000>;
> + clocks = <&vdosys1 CLK_VDO1_DISP_MIXER>,
> + <&vdosys1 CLK_VDO1_HDR_VDO_FE0>,
> + <&vdosys1 CLK_VDO1_HDR_VDO_FE1>,
> + <&vdosys1 CLK_VDO1_HDR_GFX_FE0>,
> + <&vdosys1 CLK_VDO1_HDR_GFX_FE1>,
> + <&vdosys1 CLK_VDO1_HDR_VDO_BE>,
> + <&vdosys1 CLK_VDO1_26M_SLOW>,
> + <&vdosys1 CLK_VDO1_HDR_VDO_FE0_DL_ASYNC>,
> + <&vdosys1 CLK_VDO1_HDR_VDO_FE1_DL_ASYNC>,
> + <&vdosys1 CLK_VDO1_HDR_GFX_FE0_DL_ASYNC>,
> + <&vdosys1 CLK_VDO1_HDR_GFX_FE1_DL_ASYNC>,
> + <&vdosys1 CLK_VDO1_HDR_VDO_BE_DL_ASYNC>,
> + <&topckgen CLK_TOP_ETHDR_SEL>;
> + clock-names = "mixer", "vdo_fe0", "vdo_fe1", "gfx_fe0", "gfx_fe1",
> + "vdo_be", "adl_ds", "vdo_fe0_async", "vdo_fe1_async",
> + "gfx_fe0_async", "gfx_fe1_async","vdo_be_async",
> + "ethdr_top";
> + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
> + iommus = <&iommu_vpp M4U_PORT_L3_HDR_DS>,
> + <&iommu_vpp M4U_PORT_L3_HDR_ADL>;
> + interrupts = <GIC_SPI 517 IRQ_TYPE_LEVEL_HIGH 0>; /* disp mixer */
> + resets = <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_FE0_DL_ASYNC>,
> + <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_FE1_DL_ASYNC>,
> + <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_GFX_FE0_DL_ASYNC>,
> + <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_GFX_FE1_DL_ASYNC>,
> + <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_BE_DL_ASYNC>;
> + };
> +
> +...
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