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Message-ID: <CAH=2NtwOT9K9ONZLG0G9LUvYi4h-0feJk5HuLNE0DWVg06ovCg@mail.gmail.com>
Date: Wed, 2 Mar 2022 17:47:09 +0530
From: Bhupesh Sharma <bhupesh.sharma@...aro.org>
To: Bjorn Helgaas <helgaas@...nel.org>
Cc: linux-arm-msm@...r.kernel.org, linux-pci@...r.kernel.org,
devicetree@...r.kernel.org, bhupesh.linux@...il.com,
lorenzo.pieralisi@....com, agross@...nel.org,
bjorn.andersson@...aro.org, svarbanov@...sol.com,
bhelgaas@...gle.com, linux-kernel@...r.kernel.org,
robh+dt@...nel.org, sboyd@...nel.org, mturquette@...libre.com,
linux-clk@...r.kernel.org
Subject: Re: [PATCH v2 6/7] arm64: dts: qcom: sm8150: Add pcie nodes for SM8150
Hi Bjorn,
On Wed, 2 Mar 2022 at 05:37, Bjorn Helgaas <helgaas@...nel.org> wrote:
>
> In subject, s/pcie/PCIe/
>
> Since the subject already mentions "sm8150:", maybe the "for SM8150"
> is superfluous?
>
> On Tue, Mar 01, 2022 at 12:55:10PM +0530, Bhupesh Sharma wrote:
> > Add nodes for the two PCIe controllers founds on the
> > SM8150 SoC.
>
> s/founds/found/
>
> Rewrap to fill 75 columns.
Sure, I will fix these in v3.
> > + interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
> > + <0 0 0 2 &intc 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
> > + <0 0 0 3 &intc 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
> > + <0 0 0 4 &intc 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
>
> Personally I would use INTA, INTB, etc in the comments to match the
> PCI spec usage, but grep says that's a minority view.
Right, I see that most dts (especially the qcom ones) use this
nomenclature (although I have no strong personal opinion about this).
Regards,
Bhupesh
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