linux-kernel - RE: [PATCH v2 1/2] dt-bindings: PCI: xilinx-cpm: Add Versal CPM5 Root Port

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <BY5PR02MB694774FDF8E3AA9D3576BDFAA5049@BY5PR02MB6947.namprd02.prod.outlook.com>
Date:   Thu, 3 Mar 2022 04:36:44 +0000
From:   Bharat Kumar Gogada <bharatku@...inx.com>
To:     Lorenzo Pieralisi <lorenzo.pieralisi@....com>
CC:     "linux-pci@...r.kernel.org" <linux-pci@...r.kernel.org>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
        "bhelgaas@...gle.com" <bhelgaas@...gle.com>,
        Michal Simek <michals@...inx.com>,
        "robh@...nel.org" <robh@...nel.org>
Subject: RE: [PATCH v2 1/2] dt-bindings: PCI: xilinx-cpm: Add Versal CPM5 Root
 Port

+Rob

> -----Original Message-----
> From: Lorenzo Pieralisi <lorenzo.pieralisi@....com>
> Sent: Wednesday, March 2, 2022 9:07 PM
> To: Bharat Kumar Gogada <bharatku@...inx.com>
> Cc: linux-pci@...r.kernel.org; linux-kernel@...r.kernel.org;
> bhelgaas@...gle.com; Michal Simek <michals@...inx.com>
> Subject: Re: [PATCH v2 1/2] dt-bindings: PCI: xilinx-cpm: Add Versal CPM5
> Root Port
> 
> On Tue, Feb 15, 2022 at 06:16:05PM +0530, Bharat Kumar Gogada wrote:
> > Xilinx Versal Premium series has CPM5 block which supports Root Port
> > functioning at Gen5 speed.
> >
> > Add support for YAML schemas documentation for Versal CPM5 Root Port
> driver.
> >
> > Signed-off-by: Bharat Kumar Gogada <bharat.kumar.gogada@...inx.com>
> > ---
> >  .../bindings/pci/xilinx-versal-cpm.yaml       | 47 ++++++++++++++++---
> >  1 file changed, 40 insertions(+), 7 deletions(-)
> 
> https://docs.kernel.org/devicetree/bindings/submitting-patches.html
> 
> You have to CC the devicetree ML and DT maintainers.
> 
> Thanks,
> Lorenzo
> 
> > diff --git
> > a/Documentation/devicetree/bindings/pci/xilinx-versal-cpm.yaml
> > b/Documentation/devicetree/bindings/pci/xilinx-versal-cpm.yaml
> > index 32f4641085bc..97c7229d7f91 100644
> > --- a/Documentation/devicetree/bindings/pci/xilinx-versal-cpm.yaml
> > +++ b/Documentation/devicetree/bindings/pci/xilinx-versal-cpm.yaml
> > @@ -14,17 +14,21 @@ allOf:
> >
> >  properties:
> >    compatible:
> > -    const: xlnx,versal-cpm-host-1.00
> > +    contains:
> > +      enum:
> > +        - xlnx,versal-cpm-host-1.00
> > +        - xlnx,versal-cpm5-host-1.00
> >
> >    reg:
> > -    items:
> > -      - description: Configuration space region and bridge registers.
> > -      - description: CPM system level control and status registers.
> > +    description: |
> > +      Should contain cpm_slcr, cfg registers location and length.
> > +      For xlnx,versal-cpm5-host-1.00, it should also contain cpm_csr.
> > +    minItems: 2
> > +    maxItems: 3
> >
> >    reg-names:
> > -    items:
> > -      - const: cfg
> > -      - const: cpm_slcr
> > +    minItems: 2
> > +    maxItems: 3
> >
> >    interrupts:
> >      maxItems: 1
> > @@ -95,4 +99,33 @@ examples:
> >                                 interrupt-controller;
> >                         };
> >                 };
> > +
> > +              cpm5_pcie: pcie@...d0000 {
> > +                       compatible = "xlnx,versal-cpm5-host-1.00";
> > +                       device_type = "pci";
> > +                       #address-cells = <3>;
> > +                       #interrupt-cells = <1>;
> > +                       #size-cells = <2>;
> > +                       interrupts = <0 72 4>;
> > +                       interrupt-parent = <&gic>;
> > +                       interrupt-map-mask = <0 0 0 7>;
> > +                       interrupt-map = <0 0 0 1 &pcie_intc_1 0>,
> > +                                       <0 0 0 2 &pcie_intc_1 1>,
> > +                                       <0 0 0 3 &pcie_intc_1 2>,
> > +                                       <0 0 0 4 &pcie_intc_1 3>;
> > +                       bus-range = <0x00 0xff>;
> > +                       ranges = <0x02000000 0x0 0xe0000000 0x0 0xe0000000 0x0
> 0x10000000>,
> > +                                <0x43000000 0x80 0x00000000 0x80 0x00000000 0x0
> 0x80000000>;
> > +                       msi-map = <0x0 &its_gic 0x0 0x10000>;
> > +                       reg = <0x00 0xfcdd0000 0x00 0x1000>,
> > +                             <0x06 0x00000000 0x00 0x1000000>,
> > +                             <0x00 0xfce20000 0x00 0x1000000>;
> > +                       reg-names = "cpm_slcr", "cfg", "cpm_csr";
> > +
> > +                       pcie_intc_1: interrupt-controller {
> > +                               #address-cells = <0>;
> > +                               #interrupt-cells = <1>;
> > +                               interrupt-controller;
> > +                       };
> > +               };
> >      };
> > --
> > 2.17.1
> >